參數(shù)資料
型號(hào)： AD524AE
廠(chǎng)商： Analog Devices Inc
文件頁(yè)數(shù)： 7/28頁(yè)
文件大?。?/td> 0K
描述： IC AMP INST 1MHZ PREC LN 20CLCC
產(chǎn)品變化通告： Product Discontinuance 27/Oct/2011
標(biāo)準(zhǔn)包裝： 1
放大器類(lèi)型： 儀表
電路數(shù)： 1
轉(zhuǎn)換速率： 5 V/µs
增益帶寬積： 1MHz
-3db帶寬： 1MHz
電流 - 輸入偏壓： 50nA
電壓 - 輸入偏移： 250µV
電流 - 電源： 3.5mA
電壓 - 電源，單路/雙路(±)： ±6 V ~ 18 V
工作溫度： -25°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 20-CLCC
供應(yīng)商設(shè)備封裝： 20-LCCC
包裝： 管件
AD524
Rev. F | Page 15 of 28
THEORY OF OPERATION
The AD524 is a monolithic instrumentation amplifier based
on the classic 3-op amp circuit. The advantage of monolithic
construction is the closely matched components that enhance
the performance of the input preamplifier. The preamplifier
section develops the programmed gain by the use of feedback
concepts. The programmed gain is developed by varying the
value of RG (smaller values increase the gain) while the feedback
forces the collector currents (Q1, Q2, Q3, and Q4) to be constant,
which impresses the input voltage across RG.
As RG is reduced to increase the programmed gain, the
transconductance of the input preamplifier increases to the
transconductance of the input transistors. This has three
important advantages. First, this approach allows the circuit
to achieve a very high open-loop gain of 3 × 108 at a programmed
gain of 1000, thus reducing gain-related errors to a negligible
30 ppm. Second, the gain bandwidth product, which is deter-
mined by C3 or C4 and the input transconductance, reaches
25 MHz. Third, the input voltage noise reduces to a value
determined by the collector current of the input transistors
for an RTI noise of 7 nV/√Hz at G = 1000.
INPUT PROTECTION
As interface amplifiers for data acquisition systems, instru-
mentation amplifiers are often subjected to input overloads,
that is, voltage levels in excess of the full scale for the selected
gain range. At low gains (10 or less), the gain resistor acts as a
current limiting element in series with the inputs. At high gains,
the lower value of RG does not adequately protect the inputs
from excessive currents. Standard practice is to place series
limiting resistors in each input, but to limit input current to
below 5 mA with a full differential overload (36 V) requires
over 7kΩ of resistance, which adds 10 nV√Hz of noise. To
provide both input protection and low noise, a special series
protection FET is used.
A unique FET design was used to provide a bidirectional
current limit, thereby protecting against both positive and
negative overloads. Under nonoverload conditions, three
channels (CH2, CH3, CH4) act as a resistance (≈1 kΩ) in series
with the input as before. During an overload in the positive
direction, a fourth channel, CH1, acts as a small resistance
(≈3 kΩ) in series with the gate, which draws only the leakage
current, and the FET limits IDSS. When the FET enhances under
a negative overload, the gate current must go through the small
FET formed by CH1 and when this FET goes into saturation,
the gate current is limited and the main FET goes into controlled
enhancement. The bidirectional limiting holds the maximum
input current to 3 mA over the 36 V range.
INPUT OFFSET AND OUTPUT OFFSET
Voltage offset specifications are often considered a figure of
merit for instrumentation amplifiers. While initial offset may
be adjusted to zero, shifts in offset voltage due to temperature
variations causes errors. Intelligent systems can often correct
this factor with an autozero cycle, but there are many small-
signal high-gain applications that do not have this capability.
+Vs
RG2
AD712
1/2
9.09k
1k
100
16.2k
1/2
16.2k
1.62M
1.82k
10
100
1000
G = 1, 10, 100
G = 1000
AD524
+VS
–
+
–VS
1
16
13
12
9
11
10
6
3
8
7
2
1F
–VS
1F
3
2
8
1
5
6
4
7
0
05
00-
033
+
–
+
–
Figure 33. Noise Test Circuit
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