參數(shù)資料
型號(hào)： AD5247BKSZ100-RL7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 8/20頁(yè)
文件大?。?/td> 0K
描述： IC POT DGTL 100K 128POS SC70-6
標(biāo)準(zhǔn)包裝： 1
接片： 128
電阻（歐姆）： 100k
電路數(shù)： 1
溫度系數(shù)： 標(biāo)準(zhǔn)值 45 ppm/°C
存儲(chǔ)器類型： 易失
接口： I²C
電源電壓： 2.7 V ~ 5.5 V
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 6-TSSOP，SC-88，SOT-363
供應(yīng)商設(shè)備封裝： SC-70-6
包裝： 標(biāo)準(zhǔn)包裝
配用： AD5247EVAL-ND - BOARD EVAL FOR AD5247
其它名稱： AD5247BKSZ100-RL7DKR
AD5247
Data Sheet
Rev. F | Page 16 of 20
LEVEL SHIFTING FOR BIDIRECTIONAL INTERFACE
While most legacy systems can be operated at one voltage, a
new component can be optimized at another voltage. When
two systems operate the same signal at two different voltages,
proper level shifting is needed. For instance, users can employ
a 3.3 V E2PROM to interface with a 5 V digital potentiometer. A
level shifting scheme is needed to enable a bidirectional commu-
nication so that the setting of the digital potentiometer can be
stored in and retrieved from the E2PROM. Figure 36 shows one
of the level-shifting implementations. M1 and M2 can be any
N-channel signal FETs, or if VDD falls below 2.5 V, M1 and M2
can be low threshold FETs such as the FDV301N.
E2PROM
AD5247
SDA1
SCL1
D
G
RP
3.3V
5V
S
M1
SCL2
SDA2
RP
G
S
M2
VDD1 = 3.3V
VDD2 = 5V
D
03876-
035
Figure 36. Level-Shifting for Operation at Different Potentials
ESD PROTECTION
All digital inputs are protected with a series input resistor and
parallel Zener ESD structures as shown in Figure 37. This applies
to digital input pins (SDA and SCL).
340
GND
03876-
036
LOGIC
SDA/
SCL
Figure 37. ESD Protection of Digital Pins
TERMINAL VOLTAGE OPERATING RANGE
The AD5247 VDD and GND power supply defines the boundary
conditions for proper 3-terminal digital potentiometer operation.
Supply signals present on Terminal A and Terminal W that exceed
VDD or GND are clamped by the internal forward biased diodes
A
VDD
W
GND
03876-
038
Figure 38. Maximum Terminal Voltages Set by VDD and GND
MAXIMUM OPERATING CURRENT
At low code values, the user should be aware that, due to low
resistance values, the current through the RDAC might exceed
the 5 mA limit. In Figure 39, a 5 V supply is placed on the wiper,
and the current through Terminal W and Terminal B is plotted
with respect to code. A line is also drawn denoting the 5 mA
current limit. Note that at low code values (particularly for the
5 kΩ and 10 kΩ options), the current level increases signifi-
cantly. Care should be taken to limit the current flow between
W and B in this state to a maximum continuous current of
5 mA and a maximum pulse current of no more than 20 mA.
Otherwise, degradation or possible destruction of the internal
switch contacts can occur.
CODE (Decimal)
I WB
CURRE
NT
(
mA)
0
0.01
0.1
1
10
16
32
48
64
80
96
112
128
100
5mA CURRENT LIMIT
RAB = 5k
RAB = 10k
RAB = 100k
RAB = 50k
03876-
039
Figure 39. Maximum Operating Current
POWER-UP SEQUENCE
Because the ESD protection diodes limit the voltage compliance
at Terminal A and Terminal W (see Figure 38), it is important
to power VDD/GND before applying any voltage to Terminal A
and Terminal W; otherwise, the diode is forward-biased such
that VDD is powered unintentionally and can affect the rest of the
user’s circuit. The ideal power-up sequence is in the following
order: GND, VDD, digital inputs, VA, and VW. The relative order
of powering VA and VW and the digital inputs is not important
as long as they are powered after VDD/GND.
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