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參數(shù)資料
| 型號： | AD5246BKSZ5-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 6/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DGTL RES 128POS SC70-6 |
| 標準包裝： | 1 |
| 接片： | 128 |
| 電阻（歐姆）： | 5k |
| 電路數(shù)： | 1 |
| 溫度系數(shù)： | 標準值 45 ppm/°C |
| 存儲器類型： | 易失 |
| 接口： | I²C |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 6-TSSOP，SC-88，SOT-363 |
| 供應商設(shè)備封裝： | SC-70-6 |
| 包裝： | 標準包裝 |
| 產(chǎn)品目錄頁面： | 787 (CN2011-ZH PDF) |
| 其它名稱： | AD5246BKSZ5-RL7DKR |
AD5246
Data Sheet
Rev. C | Page 14 of 16
A repeated write function gives the user flexibility to update the
RDAC output a number of times after addressing the part only
once. For example, after the RDAC has acknowledged its slave
address in write mode, the RDAC output updates on each succes-
sive byte. If different instructions are needed, the write/read mode
has to start again with a new slave address and data byte.
Similarly, a repeated read function of the RDAC is also allowed.
LEVEL SHIFTING FOR BIDIRECTIONAL INTERFACE
While most legacy systems may be operated at one voltage,
a new component may be optimized at another. When two
systems operate the same signal at two different voltages, proper
level shifting is needed. For instance, one can use a 1.8 V
E2PROM to interface with a 5 V digital potentiometer. A level
shifting scheme is needed to enable a bidirectional communi-
cation so that the setting of the digital potentiometer can be
one of the implementations. M1 and M2 can be any N channel
signal FETs, or if VDD falls below 2.5 V, M1 and M2 can be low
threshold FETs such as the FDV301N.
E2PROM
AD5246
SDA1
SCL1
D
G
RP
1.8V
5V
S
M1
SCL2
SDA2
RP
G
S
M2
VDD1 = 1.8V
VDD2 = 5V
D
03875-011
Figure 30. Level Shifting for Operation at Different Potentials
ESD PROTECTION
All digital inputs are protected with a series input resistor
and parallel Zener ESD structures, as shown in Figure 31.
This applies to the digital input pins SDA and SCL.
LOGIC
340
GND
03875-002
Figure 31. ESD Protection of Digital Pins
TERMINAL VOLTAGE OPERATING RANGE
The AD5246 VDD and GND power supply defines the boundary
conditions for proper 3-terminal digital potentiometer
operation. Supply signals present on Terminal B and
Terminal W that exceed VDD or GND are clamped by
the internal forward biased diodes (see Figure 32).
B
VDD
W
GND
03875-016
Figure 32. Maximum Terminal Voltages Set by VDD and GND
MAXIMUM OPERATING CURRENT
At low code values, the user should be aware that due to low
resistance values, the current through the RDAC may exceed
the 5 mA limit. In Figure 33, a 5 V supply is placed on the
wiper, and the current through Terminal W and Terminal B is
plotted with respect to code. A line is also drawn denoting the
5 mA current limit. Note that at low code values (particularly
for the 5 kΩ and 10 kΩ options), the current level increases
significantly. Care should be taken to limit the current flow
between W and B in this state to a maximum continuous
current of 5 mA and a maximum pulse current of no more than
20 mA. Otherwise, degradation or possible destruction of the
internal switch contacts can occur.
CODE (Decimal)
IWB
CURRENT
(mA)
0
0.01
0.1
1
10
16
32
48
64
80
96
112
128
100
5mA CURRENT LIMIT
RAB = 5k
RAB = 10k
RAB = 100k
RAB = 50k
03875-034
Figure 33. Maximum Operating Current
POWER-UP SEQUENCE
Since the ESD protection diodes limit the voltage compliance
at Terminal B and Terminal W (see Figure 32), it is important
to power VDD/GND before applying any voltage to Terminal B
and Terminal W; otherwise, the diode is forward biased such
that VDD is powered unintentionally and may affect the rest of
the user’s circuit. The ideal power-up sequence is in the follow-
ing order: GND, VDD, digital inputs, and then VB/VW. The
relative order of powering VB and VW and the digital inputs
is not important, providing they are powered after VDD/GND.
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