I2C CONTROLLER PROGRAMMING Write" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� AD5243BRMZ50
寤犲晢锛� Analog Devices Inc
鏂囦欢闋佹暩(sh霉)锛� 10/20闋�
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC POT DGTL DUAL 256POS 10-MSOP
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 50
鎺ョ墖锛� 256
闆婚樆锛堟瓙濮嗭級锛� 50k
闆昏矾鏁�(sh霉)锛� 2
婧害绯绘暩(sh霉)锛� 妯�(bi膩o)婧�(zh菙n)鍊� 35 ppm/°C
瀛樺劜鍣ㄩ鍨嬶細 鏄撳け
鎺ュ彛锛� I²C
闆绘簮闆诲锛� 2.7 V ~ 5.5 V
宸ヤ綔婧害锛� -40°C ~ 125°C
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 10-TFSOP锛�10-MSOP锛�0.118"锛�3.00mm 瀵級
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 10-MSOP
鍖呰锛� 绠′欢
鐢�(ch菐n)鍝佺洰閷勯爜闈細 787 (CN2011-ZH PDF)
閰嶇敤锛� AD5243EVAL-ND - BOARD EVAL FOR AD5243
AD5243/AD5248
Data Sheet
Rev. B | Page 18 of 20
I2C CONTROLLER PROGRAMMING
Write Bit Patterns
04109-0-022
SCL
START BY
MASTER
SDA
01
1
FRAME 1
SLAVE ADDRESS BYTE
0
1111
FRAME 2
INSTRUCTION BYTE
ACK BY
AD5243
R/W
A0
SD
X
1
9
D7
D6
D5
D4
D3
ACK BY
AD5243
FRAME 3
DATA BYTE
1
9
X
STOP BY
MASTER
9
D2
D1
D0
ACK BY
AD5243
X
Figure 45. Writing to the RDAC Register鈥擜D5243
04109-0-023
SCL
START BY
MASTER
SDA
01
1
FRAME 1
SLAVE ADDRESS BYTE
0
1
AD1 AD0
FRAME 2
INSTRUCTION BYTE
ACK BY
AD5248
R/W
A0
SD
X
1
9
D7
D6
D5
D4
D3
ACK BY
AD5248
FRAME 3
DATA BYTE
1
9
X
STOP BY
MASTER
9
D2
D1
D0
ACK BY
AD5248
X
Figure 46. Writing to the RDAC Register鈥擜D5248
Read Bit Patterns
04109-0-024
SCL
START BY
MASTER
STOP BY
MASTER
SDA
01
1
FRAME 1
SLAVE ADDRESS BYTE
01
1
FRAME 2
RDAC REGISTER
ACK BY
AD5243
R/W
D7
D6
D4
D3
D2
D1
D0
1
9
NO ACK
BY MASTER
9
D5
Figure 47. Reading Data from a Previously Selected RDAC Register in Write Mode鈥擜D5243
04109-0-025
SCL
START BY
MASTER
SDA
01
1
FRAME 1
SLAVE ADDRESS BYTE
0
1
AD1 AD0
FRAME 2
RDAC REGISTER
ACK BY
AD5248
R/W
D7
D6
D4
D3
D2
D1
D0
1
99
D5
STOP BY
MASTER
NO ACK
BY MASTER
Figure 48. Reading Data from a Previously Selected RDAC Register in Write Mode鈥擜D5248
Multiple Devices on One Bus (Applies Only to AD5248)
Figure 49 shows four AD5248 devices on the same serial bus.
Each has a different slave address because the states of their
AD0 and AD1 pins are different. This allows each device on the
bus to be written to or read from independently. The master
device output bus line drivers are open-drain pull-downs in a
fully I2C-compatible interface.
SDA
AD1
AD0
MASTER
SCL
AD5248
SDA
AD1
AD0
SCL
AD5248
SDA
AD1
AD0
SCL
AD5248
SDA
5V
RP
5V
AD1
AD0
SCL
AD5248
04109-0-026
Figure 49. Multiple AD5248 Devices on One I2C Bus
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AD5243BRMZ50-RL7 鍔熻兘鎻忚堪:IC DGTL POT DUAL 50K 10-MSOP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - 鏁�(sh霉)瀛楅浕浣嶅櫒 绯诲垪:- 妯�(bi膩o)婧�(zh菙n)鍖呰:3,000 绯诲垪:DPP 鎺ョ墖:32 闆婚樆锛堟瓙濮嗭級:10k 闆昏矾鏁�(sh霉):1 婧害绯绘暩(sh霉):妯�(bi膩o)婧�(zh菙n)鍊� 300 ppm/°C 瀛樺劜鍣ㄩ鍨�:闈炴槗澶� 鎺ュ彛:3 绶氫覆琛岋紙鑺墖閬告搰锛岄仦澧�锛屽/娓涳級 闆绘簮闆诲:2.5 V ~ 6 V 宸ヤ綔婧害:-40°C ~ 85°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:8-WFDFN 瑁搁湶鐒婄洡 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:8-TDFN锛�2x3锛� 鍖呰:甯跺嵎 (TR)
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