V
參數(shù)資料
型號(hào)： AD5233BRUZ50
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 27/32頁(yè)
文件大?。?/td> 0K
描述： IC POT QUAD 50K 64POS 24-TSSOP
標(biāo)準(zhǔn)包裝： 62
接片： 64
電阻（歐姆）： 50k
電路數(shù)： 4
溫度系數(shù)： 標(biāo)準(zhǔn)值 600 ppm/°C
存儲(chǔ)器類型： 非易失
接口： 4 線 SPI（芯片選擇）
電源電壓： 2.7 V ~ 5.5 V，±2.25 V ~ 2.75 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 24-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 24-TSSOP
包裝： 管件
產(chǎn)品目錄頁(yè)面： 787 (CN2011-ZH PDF)
AD5233
Rev. B | Page 4 of 32
Parameter
Symbol
Conditions
Min
Max
Unit
POWER SUPPLIES
Single-Supply Power Range
VDD
VSS = 0 V
2.7
5.5
V
Dual-Supply Power Range
VDD/VSS
±2.5
±2.75
V
Positive Supply Current
IDD
VIH = VDD or VIL = GND
3.5
10
μA
Negative Supply Current
ISS
VIH = VDD or VIL = GND,
VDD = 2.5 V, VSS = 2.5 V
0.55
10
μA
EEMEM Store Mode Current
IDD (store)
VIH = VDD or VIL = GND,
VSS = 0, ISS
≈ 0
40
mA
ISS (store)
VDD = 2.5 V, VSS = 2.5 V
40
mA
EEMEM Restore Mode Current7
IDD (restore)
VIH = VDD or VIL = GND,
VSS = GND, ISS
≈ 0
0.3
3
9
mA
ISS (restore)
VDD = 2.5 V, VSS = 2.5 V
0.3
3
9
mA
Power Dissipation8
PDISS
VIH = VDD or VIL = GND
0.018
0.05
mW
Power Supply Sensitivity5
PSS
VDD = 5 V ± 10%
0.002
0.01
%/%
DYNAMIC CHARACTERISTICS5, 9
Bandwidth
BW
3 dB, RAB = 10 kΩ/50 kΩ/100 kΩ
630/135/66
kHz
Total Harmonic Distortion
THDW
VA = 1 V rms, VB = 0 V, f = 1 kHz,
RAB = 10 kΩ
0.04
%
VA = 1 V rms, VB = 0 V, f = 1 kHz,
RAB = 50 kΩ, 100 kΩ
0.015
%
VW Settling Time
tS
VA = VDD, VB = 0 V,
VW = 0.50% error band,
Code 0x000 to Code 0x200
for RAB = 10 kΩ/50 kΩ/100 kΩ
0.6/2.2/3.8
μs
Resistor Noise Voltage
eN_WB
RWB = 5 kΩ, f = 1 kHz
9
nV/√Hz
Crosstalk (CW1/CW2)
CT
VA = VDD, VB = 0 V, measure VW
with adjacent RDAC making
the full-scale code change
1
nV/sec
Analog Crosstalk (CW1/CW2)
CTA
VDD = VA1 = +2.5 V,
VSS = VB1 = 2.5 V,
measure VW1 with VW2 = 5 V p-p
@ f = 10 kHz, Code 1 = 0x20,
Code 2 = 0x3F, RAB = 10 kΩ/
50 kΩ/100 kΩ
86/73/68
dB
1 Typicals represent average readings at 25°C and VDD = 5 V.
2 Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. IW > 50 μA @ VDD = 2.7 V for the RAB = 10 kΩ version, IW > 50 μA for the
RAB = 50 kΩ, and IW > 25 μA for the RAB = 100 kΩ version (see Figure 25).
3 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output ADC. VA = VDD and VB = VSS. DNL specification limits of
1 LSB minimum are guaranteed monotonic operating conditions (see Figure 26).
4 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables ground-
referenced bipolar signal adjustment.
5 Guaranteed by design and not subject to production test.
6 Common-mode leakage current is a measure of the dc leakage from Terminal B and Terminal W to a common-mode bias level of VDD/2.
7 EEMEM restore mode current is not continuous. Current is consumed while EEMEM locations are read and transferred to the RDAC register (see Figure 22). To
minimize power dissipation, a NOP instruction should be issued immediately after Instruction 1 (0x1).
8 Power dissipation is calculated by PDISS = (IDD × VDD) + (ISS × VSS).
9 All dynamic characteristics use VDD = 2.5 V and VSS = 2.5 V.
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