
AD5231
Data Sheet
Rev. D | Page 6 of 28
Timing Diagrams
CLK
CPOL = 1
B24*
B23–MSB
B0–LSB
B23–MSB
HIGH
OR LOW
HIGH
OR LOW
B23
B0
B0–LSB
RDY
CPHA = 1
* NOT DEFINED, BUT NORMALLY LSB OF CHARACTER PREVIOUSLY TRANSMITTED.
THE CPOL = 1 MICROCONTROLLER COMMAND ALIGNS THE INCOMING DATA TO THE POSITIVE EDGE OF THE CLOCK.
SDO
SDI
CS
t2
t1
t5
t4
t7
t6
t10
t8
t14
t11
t9
t12
t3
t13
t17
t15
t16
02
73
9-
0
03
Figure 3. CPHA = 1 Timing Diagram
CLK
CPOL = 0
B23–MSB OUT
B0–LSB
SDO
B23–MSB IN
B23
B0
HIGH
OR LOW
HIGH
OR LOW
B0–LSB
SDI
RDY
CPHA = 0
* NOT DEFINED, BUT NORMALLY MSB OF CHARACTER PREVIOUSLY RECEIVED.
THE CPOL = 0 MICROCONTROLLER COMMAND ALIGNS THE INCOMING DATA TO THE POSITIVE EDGE OF THE CLOCK.
*
CS
t2
t1
t4
t5
t7
t6
t10
t8
t14
t11
t9
t12
t3
t13
t17
t15
t16
02
73
9-
00
4
Figure 4. CPHA = 0 Timing Diagram