參數(shù)資料
型號(hào)： AD5228BUJZ50-RL7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 6/20頁(yè)
文件大小： 0K
描述： IC DGTL POT 50K UP/DN TSOT23-8
標(biāo)準(zhǔn)包裝： 3,000
接片： 32
電阻（歐姆）： 50k
電路數(shù)： 1
溫度系數(shù)： 標(biāo)準(zhǔn)值 35 ppm/°C
存儲(chǔ)器類型： 易失
接口： 2 線按鈕
電源電壓： 2.7 V ~ 5.5 V
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： SOT-23-8 薄型，TSOT-23-8
供應(yīng)商設(shè)備封裝： TSOT-23-8
包裝： 帶卷 (TR)
配用： EVAL-AD5228EBZ-ND - BOARD EVAL FOR AD5228 DGTL POT
AD5228
Rev. A | Page 14 of 20
LAYOUT AND POWER SUPPLY BIASING
POWER-UP AND POWER-DOWN SEQUENCES
It is always a good practice to use compact, minimum lead
length layout design. The leads to the input should be as direct
as possible with a minimum conductor length. Ground paths
should have low resistance and low inductance. It is also good
practice to bypass the power supplies with quality capacitors.
Low ESR (equivalent series resistance) 1 μF to 10 μF tantalum
or electrolytic capacitors should be applied at the supplies to
minimize any transient disturbance and to filter low frequency
ripple. Figure 39 illustrates the basic supply bypassing configu-
ration for the AD5228.
Because of the ESD protection diodes that limit the voltage
compliance at Terminals A, B, and W (Figure 39), it is
important to power on VDD before applying any voltage to
Terminals A, B, and W. Otherwise, the diodes are forward-
biased such that VDD is powered on unintentionally and can
affect other parts of the circuit. Similarly, VDD should be
powered down last. The ideal power-on sequence is in the
following order: GND, VDD, and VA/B/W. The order of powering
VA, VB, and VW is not important as long as they are powered on
after VDD. The states of the PU and PD pins can be logic high or
floating, but they should not be logic low during power-on.
04422-0-041
VDD
+
GND
AD5228
C2
10
μF
C1
0.1
μF
Figure 40. Power Supply Bypassing
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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