參數(shù)資料
型號(hào): AD5227BUJZ50-RL7
廠商: Analog Devices Inc
文件頁數(shù): 13/16頁
文件大?。?/td> 0K
描述: IC DGTL POT 50K UP/DN TSOT23-8
標(biāo)準(zhǔn)包裝: 1
接片: 64
電阻(歐姆): 50k
電路數(shù): 1
溫度系數(shù): 標(biāo)準(zhǔn)值 35 ppm/°C
存儲(chǔ)器類型: 易失
接口: 3 線串行(芯片選擇,增/減)
電源電壓: 2.7 V ~ 5.5 V
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: SOT-23-8 薄型,TSOT-23-8
供應(yīng)商設(shè)備封裝: TSOT-23-8
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: AD5227BUJZ50-RL7DKR
AD5227
Rev. B | Page 6 of
16
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
04419-0-003
AD5227
TOP VIEW
(Not to Scale)
CLK
1
U/D
2
A
3
GND
4
VDD
CS
B
W
8
7
6
5
Figure 5. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
CLK
Clock Input. Each clock pulse executes the step-up or step-down of the resistance. The direction is determined
by the state of the U/D pin. CLK is a negative-edge trigger. Logic high signal can be higher than VDD, but lower
than 5.5 V.
2
U/D
Up/Down Selections. Logic 1 selects up and Logic 0 selects down. U can be higher than VDD, but lower than 5.5 V.
3
A
Resistor Terminal A. GND ≤ VA ≤ VDD.
4
GND
Common Ground.
5
W
Wiper Terminal W. GND ≤ VW ≤ VDD.
6
B
Resistor Terminal B. GND ≤ VB ≤ VDD.
7
CS
Chip Select. Active Low. Logic high signal can be higher than VDD, but lower than 5.5 V.
8
VDD
Positive Power Supply, 2.7 V to 5.5 V.
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