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參數(shù)資料
| 型號(hào)： | AD5203ARUZ10-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 3/12頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC POT DGTL QUAD 64POS 24TSSOP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 接片： | 64 |
| 電阻（歐姆）： | 10k |
| 電路數(shù)： | 4 |
| 溫度系數(shù)： | 標(biāo)準(zhǔn)值 700 ppm/°C |
| 存儲(chǔ)器類(lèi)型： | 易失 |
| 接口： | 4 線 SPI（芯片選擇） |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 24-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-TSSOP |
| 包裝： | 帶卷 (TR) |
AD5203
–11–
REV. 0
The data setup and data hold times in the specification table
determine the data valid time requirements. The last eight bits
of the data word entered into the serial register are held when
CS returns high. At the same time CS goes high it gates the
address decoder which enables one of four positive edge trig-
gered RDAC latches, see Figure 36 detail.
RDAC 1
RDAC 2
RDAC 4
AD5203
SDI
CLK
CS
ADDR
DECODE
SERIAL
REGISTER
Figure 36. Equivalent Input Control Logic
The target RDAC latch is loaded with the last six bits of the
serial data word completing one RDAC update. Four separate
8-bit data words must be clocked in to change all four VR
settings.
SERIAL
REGISTER
SDI
CK
RS
D
Q
SHDN
CS
CLK
RS
SDO
Figure 37. Detail, SDO Output Schematic of the AD5203
All digital inputs are protected with a series input resistor and
parallel Zener ESD structure shown in Figure 38. Applies to
digital input pins
CS, SDI, SDO, RS, SHDN, CLK.
1k
LOGIC
Figure 38. Equivalent ESD Protection Circuit
DYNAMIC CHARACTERISTICS
The total harmonic distortion plus noise (THD+N) measures
0.003% using an offset ground with a rail-to-rail OP279 invert-
ing op amp test circuit, see Figure 30. Figure 15 plots THD
versus frequency for both inverting and noninverting amplifier
topologies. Thermal noise is primarily Johnson noise, typically
9 nV/
√Hz for the 10 k version measured at 1 kHz. For the
100 k
device, thermal noise measures 29 nV/√Hz. Channel-to-
channel crosstalk measures less than –65 dB at f = 100 kHz. To
achieve this isolation, the extra ground pins (AGND) located
between the potentiometer terminals (A, B, W) must be con-
nected to circuit ground. The AGND and DGND pins should
be at the same voltage potential. Any unused potentiometers in
a package should be connected to ground. Power supply rejec-
tion is typically –50 dB at 10 kHz (care is needed to minimize
power supply ripple injection in high accuracy applications).
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| AD5203ARZ10 | 功能描述:IC POT DGTL QUAD 64POS 24SOIC RoHS:是 類(lèi)別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)字電位器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 接片:256 電阻（歐姆）:100k 電路數(shù):1 溫度系數(shù):標(biāo)準(zhǔn)值 35 ppm/°C 存儲(chǔ)器類(lèi)型:非易失 接口:3 線串口 電源電壓:2.7 V ~ 5.25 V 工作溫度:-40°C ~ 85°C 安裝類(lèi)型:表面貼裝 封裝/外殼:8-WDFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:8-TDFN-EP（3x3） 包裝:剪切帶 (CT) 產(chǎn)品目錄頁(yè)面:1399 (CN2011-ZH PDF) 其它名稱(chēng):MAX5423ETA+TCT |
| AD5203ARZ100 | 功能描述:IC POT DGTL QUAD 64POS 24SOIC RoHS:是 類(lèi)別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)字電位器 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:XDCP™ 接片:256 電阻（歐姆）:100k 電路數(shù):1 溫度系數(shù):標(biāo)準(zhǔn)值 ±300 ppm/°C 存儲(chǔ)器類(lèi)型:非易失 接口:I²C（設(shè)備位址） 電源電壓:2.7 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:14-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:14-TSSOP 包裝:帶卷 (TR) |
| AD5203ARZ100-REEL | 功能描述:IC POT DGTL QUAD 64POS 24SOIC RoHS:是 類(lèi)別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)字電位器 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:DPP 接片:32 電阻（歐姆）:10k 電路數(shù):1 溫度系數(shù):標(biāo)準(zhǔn)值 300 ppm/°C 存儲(chǔ)器類(lèi)型:非易失 接口:3 線串行（芯片選擇，遞增，增/減） 電源電壓:2.5 V ~ 6 V 工作溫度:-40°C ~ 85°C 安裝類(lèi)型:表面貼裝 封裝/外殼:8-WFDFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:8-TDFN（2x3） 包裝:帶卷 (TR) |
| AD5204 | 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:256-Position and 33-Position Digital Potentiometers |
| AD5204_10 | 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:4-/6-Channel Digital Potentiometers |
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