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參數(shù)資料
| 型號： | AD5175BCPZ-10-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 18/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC RHEOSTAT 5V 50-TP 1024 10MSOP |
| 標準包裝： | 1 |
| 接片： | 1024 |
| 電阻（歐姆）： | 10k |
| 電路數(shù)： | 1 |
| 溫度系數(shù)： | 標準值 35 ppm/°C |
| 存儲器類型： | 非易失 |
| 接口： | I²C |
| 電源電壓： | 2.7 V ~ 5.5 V，±2.5 V ~ 2.75 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 10-MSOP |
| 包裝： | 標準包裝 |
| 其它名稱： | AD5175BCPZ-10-RL7DKR |
AD5175
Rev. A | Page 7 of 20
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VDD 11
VSS
2
A
3
W
4
RESET
10
9
8
SCL
7
5
EXT_CAP
SDA
6
GND
AD5175
TOP VIEW
(Not to Scale)
ADDR
08
719
-00
4
*LEAVE FLOATING OR CONNECTED TO VSS.
ADDR
VDD 1
VSS
2
A
3
W
4
RESET
10
9
8
SCL
7
5
EXT_CAP
SDA
6 GND
AD5175
(EXPOSED
PAD)*
08
71
9-
1
03
Figure 4. MSOP Pin Configuration
Figure 5. LFCSP Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
VDD
Positive Power Supply. Decouple this pin with 0.1 μF ceramic capacitors and 10 μF capacitors.
2
A
Terminal A of RDAC. VSS ≤ VA ≤ VDD.
3
W
Wiper Terminal of RDAC. VSS ≤ VW ≤ VDD.
4
VSS
Negative Supply. Connect to 0 V for single-supply applications. Decouple this pin with 0.1 μF ceramic capacitors
and 10 μF capacitors.
5
EXT_CAP
External Capacitor. Connect a 1 μF capacitor between EXT_CAP and VSS. This capacitor must have a voltage
rating of ≥7 V.
6
GND
Ground Pin, Logic Ground Reference.
7
RESET
Hardware Reset Pin. Refreshes the RDAC register with the contents of the 50-TP memory register. Factory
default loads midscale until the first 50-TP wiper memory location is programmed. RESET is active low. Tie RESET
to VDD if not used.
8
SDA
Serial Data Line. This pin is used in conjunction with the SCL line to clock data into or out of the 16-bit input
registers. It is a bidirectional, open-drain data line that should be pulled to the supply with an external
pull-up resistor.
9
SCL
Serial Clock Line. This pin is used in conjunction with the SDA line to clock data into or out of the 16-bit
input registers.
10
ADDR
Tristate Address Input. Sets the two least significant bits (Bit A1, Bit A0) of the 7-bit slave address (see Table 6).
EPAD
Exposed Pad
Leave floating or connected to VSS
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