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| 型號： | AD5171EVAL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 9/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD5171 |
| 標準包裝： | 1 |
| 主要目的： | 數(shù)字電位器 |
| 已用 IC / 零件： | AD5171 |
| 已供物品： | 板 |
| 相關產(chǎn)品： | AD5171BRJZ5-R2DKR-ND - IC DGTL POT OTP 5K 12C SOT23-8 AD5171BRJZ50-R2DKR-ND - IC DGTL POT OTP 50K I2C SOT23-8 AD5171BRJZ10-R2DKR-ND - IC DGTL POT OTP 10K I2C SOT23-8 AD5171BRJZ100R2DKR-ND - IC DGTL POT OTP 100K I2C SOT23-8 AD5171BRJZ5-R7-ND - IC DGTL POT OTP 5K SOT23-8 AD5171BRJZ50-R7-ND - IC DGTL POT OTP 50K SOT23-8 AD5171BRJZ100-R7-ND - IC DGTL POT OTP 100K SOT23-8 AD5171BRJZ10-R7-ND - IC DGTL POT OTP 10K SOT23-8 AD5171BRJZ50-R2CT-ND - IC DGTL POT OTP 50K I2C SOT23-8 AD5171BRJZ5-R2CT-ND - IC DGTL POT OTP 5K 12C SOT23-8 更多... |
AD5171
Rev. D | Page 17 of 24
Table 10. SDA Bits Definitions and Descriptions
Bit
Description
S
Start Condition.
P
Stop Condition.
A
Acknowledge.
AD0
I2C Device Address Bit. Allows a maximum of two AD5171s to be addressed.
X
Don’t Care.
T
OTP Programming Bit. Logic 1 programs the wiper position permanently.
D5, D4, D3, D2, D1, D0
Data Bits.
E1, E0
OTP Validation Bits:
0, 0 = Ready to Program.
0, 1 = Test Fuse Not Blown Successfully. For factory setup checking purpose only. Users should not see these
combinations.
1, 0 = Fatal Error. Do not retry. Discard the unit.
1, 1 = Programmed Successfully. No further adjustments are possible.
I2C CONTROLLER PROGRAMMING
Write Bit Patterns
SDA
SCL
0
1
0
11
0 AD0 R/W
0
X
XD5
D4
D3
D2
D1
D0
91
9
STOP BY
MASTER
FRAME 1
DATA BYTE
FRAME 2
INSTRUCTION BYTE
FRAME 1
SLAVE ADDRESS BYTE
START BY
MASTER
ACK. BY
AD5171
ACK. BY
AD5171
ACK. BY
AD5171
03
437
-03
5
Figure 35. Writing to the RDAC Register
SDA
SCL
0
1
0
11
0 AD0 R/W
1X
X
D5
D4D3
D2D1
D0
91
9
STOP BY
MASTER
FRAME 1
DATA BYTE
FRAME 2
INSTRUCTION BYTE
FRAME 1
SLAVE ADDRESS BYTE
START BY
MASTER
ACK. BY
AD5171
ACK. BY
AD5171
ACK. BY
AD5171
03
43
7
-03
6
Figure 36. Activating One-Time Programming
Read Bit Pattern
SDA
SCL
0
1
0
11
0 AD0
E1
E0
D5
D4
D3
D2
D1
D0
91
9
R/W
STOP BY
MASTER
FRAME 2
RDAC REGISTER
FRAME 1
SLAVE ADDRESS BYTE
START BY
MASTER
NO ACK. BY
MASTER
ACK. BY
AD5171
03
43
7-
03
7
Figure 37. Reading Data from RDAC Register
I2C-COMPATIBLE 2-WIRE SERIAL BUS
For users who prefer to use external controllers, the AD5171
can be controlled via an I2C-compatible serial bus; the part is
connected to this bus as a slave device. The following section
describes how the 2-wire I2C serial bus protocol operates (see
The master initiates data transfer by establishing a start condition,
which is when SDA goes from high to low while SCL is high
address byte, which consists of the 6 MSBs as a slave address
defined as 010110. The next bit is AD0, which is an I2C device
address bit. Depending on the states of their AD0 bits, two
AD5171s can be addressed on the same bus (see Figure 38). The
last LSB is the R/W bit, which determines whether data is read
from, or written to, the slave device.
The slave address corresponding to the transmitted address bit
responds by pulling the SDA line low during the 9th clock pulse
(this is termed the acknowledge bit). At this stage, all other
devices on the bus remain idle while the selected device waits
for data to be written to, or read from, its serial register.
The write operation contains one instruction byte more than
the read operation. The instruction byte in the write mode
follows the slave address byte. The MSB of the instruction byte
labeled T is the one-time programming bit. After acknowledging
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