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| 型號： | AD5171BRJZ10-R2 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 11/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DGTL POT OTP 10K I2C SOT23-8 |
| 標準包裝： | 1 |
| 接片： | 64 |
| 電阻（歐姆）： | 10k |
| 電路數(shù)： | 1 |
| 溫度系數(shù)： | 標準值 35 ppm/°C |
| 存儲器類型： | 非易失 |
| 接口： | I²C（設(shè)備位址） |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | SOT-23-8 |
| 供應(yīng)商設(shè)備封裝： | SOT-23-8 |
| 包裝： | 標準包裝 |
| 配用： | AD5171EVAL-ND - BOARD EVAL FOR AD5171 |
| 其它名稱： | AD5171BRJZ10-R2DKR |
AD5171
Rev. D | Page 19 of 24
APPLICATIONS INFORMATION
DAC
It is common to buffer the output of the digital potentiometer as
a DAC unless the load is much larger than RWB. The buffer can
impede conversion and deliver higher current, if needed.
GND
VIN
VOUT
1
5V
2
3
VO
AD8601
5V
A
W
B
U1
AD1582
A1
AD5171
U2
03
43
7-
03
9
Figure 39. Programmable Voltage Reference (DAC)
GAIN CONTROL COMPENSATION
The digital potentiometers are commonly used in gain
controls or sensor transimpedance amplifier signal conditioning
applications (see Figure 40). To avoid gain peaking, or in worst-
case oscillation due to step response, a compensation capacitor
is needed. In general, C2 in the range of a few picofarads to a
few tenths of a picofarad is adequate for the compensation.
U1
C2
4.7pF
A
B
W
R2 100k
VO
VI
R1
47k
0
34
37-
0
40
Figure 40. Typical Noninverting Gain Amplifier
PROGRAMMABLE VOLTAGE SOURCE WITH
BOOSTED OUTPUT
For applications that require high current adjustment, such as a
laser diode driver or tunable laser, a boosted voltage source can
be considered (see Figure 41).
+V
W
SIGNAL
CC RBIAS
LD
VIN
A
B
VOUT
U1
AD5171
U3 2N7002
AD8601
U2
–V
IL
0
343
7-
0
41
Figure 41. Programmable Booster Voltage Source
In this circuit, the inverting input of the op amp forces the VOUT
to be equal to the wiper voltage set by the digital potentiometer.
The load current is then delivered by the supply via the NCh
FET N1. N1 power handling must be adequate to dissipate
(VI VO) × IL power. This circuit can source a maximum of
100 mA with a 5 V supply. For precision applications, a voltage
applied at Terminal A of the digital potentiometer.
LEVEL SHIFTING FOR DIFFERENT VOLTAGE
OPERATION
If the SCL and SDA signals come from a low voltage logic
controller and are below the minimum VIH level (0.7 V × VDD),
level shift the signals for read/write communications between
the AD5171 and the controller. Figure 42 shows one of the
implementations. For example, when SDA1 is at 2.5 V, M1 turns
off, and SDA2 becomes 5 V. When SDA1 is at 0 V, M1 turns on,
and SDA2 approaches 0 V. As a result, proper level shifting is
established. M1 and M2 should be low threshold N-Ch power
MOSFETs, such as FDV301N.
2.5V
CONTROLLER
2.7V–5.5V
AD5171
Rp
VDD1 = 2.5V
VDD2 = 5V
G
S
D
M1
S
D
M2
SDA1
SCL1
SDA2
SCL2
03
43
7-
0
42
Figure 42. Level Shifting for Different Voltage Operation
RESISTANCE SCALING
The AD5171 offers 5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ nominal
resistances. For users who need to optimize the resolution with
an arbitrary full range resistance, the following techniques can
be used. By paralleling a discrete resistor, a proportionately lower
voltage appears at Terminal A to Terminal B, which is applicable
only to the voltage divider mode (see Figure 43).
This translates into a finer degree of precision because the step
size at Terminal W is smaller. The voltage can be found as
DD
AB
W
V
D
R2
R
R3
R2
R
D
V
×
+
=
64
||
)
||
(
)
(
(5)
R1
R2
B
A
VDD
R3
W
03
43
7-
04
3
Figure 43. Lowering the Nominal Resistance
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