VDD
參數(shù)資料
型號(hào): AD5170BRMZ50
廠商: Analog Devices Inc
文件頁數(shù): 22/24頁
文件大?。?/td> 0K
描述: IC POT DGTL 50K 256POS 10-MSOP
標(biāo)準(zhǔn)包裝: 50
接片: 256
電阻(歐姆): 50k
電路數(shù): 1
溫度系數(shù): 標(biāo)準(zhǔn)值 35 ppm/°C
存儲(chǔ)器類型: 易失
接口: I²C,2 線串口
電源電壓: 2.7 V ~ 5.5 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 10-TFSOP,10-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 10-MSOP
包裝: 管件
產(chǎn)品目錄頁面: 786 (CN2011-ZH PDF)
AD5170
Rev. G | Page 7 of 24
TIMING CHARACTERISTICS: 2.5 kΩ, 10 kΩ, 50 kΩ, AND 100 kΩ
VDD = 5 V ± 10% or 3 V ± 10%, VA = VDD; VB = 0 V, 40°C < TA < +125°C, unless otherwise noted.
Table 3.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
I2C INTERFACE TIMING CHARACTERISTICS1 (SPECIFICATIONS
APPLY TO ALL PARTS)
SCL Clock Frequency
fSCL
400
kHz
tBUF Bus Free Time Between Stop and Start
t1
1.3
μs
tHD;STA Hold Time (Repeated Start)
t2
After this period, the first clock
pulse is generated
0.6
μs
tLOW Low Period of SCL Clock
t3
1.3
μs
tHIGH High Period of SCL Clock
t4
0.6
μs
tSU;STA Setup Time for Repeated Start Condition
t5
0.6
μs
tHD;DAT Data Hold Time2
t6
0.9
μs
tSU;DAT Data Setup Time
t7
100
ns
tF Fall Time of Both SDA and SCL Signals
t8
300
ns
tR Rise Time of Both SDA and SCL Signals
t9
300
ns
tSU;STO Setup Time for Stop Condition
t10
0.6
μs
OTP Program Time
t11
400
ms
1 See Figure 2 for locations of measured values.
2 The maximum tHD;DAT must be met only if the device does not stretch the low period (tLOW) of the SCL signal.
Timing Diagram
04
104
-04
4
t1
t2
t3
t8
t9
t6
t4
t7
t5
t2
t10
PS
S
SCL
SDA
P
Figure 2. I2C Interface Detailed Timing Diagram
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