參數(shù)資料
型號： AD5065BRUZ-REEL7
廠商： Analog Devices Inc
文件頁數(shù)： 14/28頁
文件大?。?/td> 0K
描述： IC DAC DUAL 16BIT SPI 14TSSOP
產(chǎn)品培訓(xùn)模塊： Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝： 1,000
系列： nanoDAC™
設(shè)置時間： 10.7µS
位數(shù)： 16
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 2
電壓電源： 單電源
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 14-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 14-TSSOP
包裝： 帶卷 (TR)
輸出數(shù)目和類型： 2 電壓，雙極
采樣率（每秒）： *
AD5025/AD5045/AD5065
Rev. 0 | Page 21 of 28
CLEAR CODE REGISTER
The AD5025/AD5045/AD5065 have a hardware CLR pin that
is an asynchronous clear input. The CLR input is falling edge sensi-
tive. Bringing the CLR line low clears the contents of the input
register and the DAC registers to the data contained in the user-
configurable CLR register, and sets the analog outputs accordingly
(see Table 13). This function can be used in system calibration
to load zero scale, midscale, or full scale to all channels together.
These clear code values are user-programmable by setting two
bits, Bit DB1 and Bit DB0, in the input register (see Table 13).
The default setting clears the outputs to 0 V. Command 0101 is
reserved for loading the clear code register (see Table 8).
Table 13. Clear Code Register
Clear Code Register
DB1 (CR1)
DB0 (CR0)
Clears to Code
0
0x0000
0
1
0x8000
1
0
0xFFFF
1
No operation
The part exits clear code mode on the 32nd falling edge of the
next write to the part. If CLR is activated during a write sequence,
the write is aborted.
The CLR pulse activation time, the falling edge of CLR to when
the output starts to change, is typically 10.6 μs (see Figure 31).
See Table 14 for contents of the input register during the
loading clear code register operation.
LDAC FUNCTION
Hardware LDAC Pin
The outputs of all DACs can be updated simultaneously using
the hardware LDAC pin. The LDAC pin can be used in
synchronous or asynchronous mode, as shown in Figure 3.
Synchronous LDAC: LDAC is held low. After new data is read,
the DAC registers are updated on the falling edge of the 32nd
SCLK pulse. LDAC can be permanently low or pulsed in
standalone mode. LDAC cannot be tied permanently low in
daisy-chain mode.
Asynchronous LDAC: LDAC is held high and pulsed. The outputs
are not updated at the same time that the input registers are
written to. When LDAC goes low, the DAC registers are updated
with the contents of the input register.
Software LDAC Function
Alternatively, the outputs of all DACs can be updated simulta-
neously using the software LDAC function by writing to Input
Register n (see Table 7) and updating all DAC registers.
Command 0010 is reserved for this software LDAC function.
The LDAC register gives the user extra flexibility and control
over the hardware LDAC pin (see Table 16). Setting the LDAC
bit register (DB0 to DB3) to 0 for a DAC channel means that
this channel update is controlled by the hardware LDAC pin.
If DB0 or DB3 is set to 1, this channel updates synchronously.
The part effectively sees the hardware LDAC pin as being tied
low (see Table 15 for the LDAC register mode of operation).
This flexibility is useful in applications where the user wants to
simultaneously update select channels while the rest of the
channels are synchronously updating.
Table 14. 32-Bit Input Register Contents for Clear Code Function
MSB
LSB
DB31 to DB28
DB27
DB26
DB25
DB24
DB23
DB22
DB21
DB20
DB2 to DB19
DB1
DB0
X
0
1
0
1
X
1/0
Don’t cares
Command bits (C3 to C0)
Address bits (A3 to A0)
Don’t cares
Clear code register
(CR1 to CR0)
Table 15. LDAC Overwrite Definitions
Load DAC Register
LDAC Bits (DB3 and DB0)
LDAC Pin
LDAC Operation
0
1, 0
Determined by LDAC pin.
1
X1
DAC channels update, overrides the LDAC pin. DAC channels see LDAC as 0.
1 X = don’t care.
Table 16. 32-Bit Input Register Contents for LDAC Overwrite Function
MSB
LSB
DB31 to DB28
DB27
DB26
DB25
DB24
DB23
DB22
DB21
DB20
DB4 to DB19
DB3
DB2
DB1
DB0
X
0
1
0
X
DAC B
X
DAC A
Don’t cares
Command bits (C3 to C0)
Address bits (A3 to A0)—don’t cares
Don’t cares
Set LDAC bits to 1 to override LDAC pin
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