VDD = 2.7 V to 5.5 V; all specifica" />
參數(shù)資料
型號: AD5063BRMZ-REEL7
廠商: Analog Devices Inc
文件頁數(shù): 16/20頁
文件大小: 0K
描述: IC DAC 16BIT 2.7-5.5V 10MSOP
產(chǎn)品培訓模塊: Data Converter Fundamentals
DAC Architectures
標準包裝: 1,000
系列: nanoDAC™
設(shè)置時間: 4µs
位數(shù): 16
數(shù)據(jù)接口: 串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 10-TFSOP,10-MSOP(0.118",3.00mm 寬)
供應商設(shè)備封裝: 10-MSOP
包裝: 帶卷 (TR)
輸出數(shù)目和類型: 1 電壓,單極;1 電壓,雙極
采樣率(每秒): 333k
AD5063
Rev. C | Page 5 of
20
TIMING CHARACTERISTICS
VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
Unit
Test Conditions/Comments
33
ns min
SCLK cycle time
t2
5
ns min
SCLK high time
t3
3
ns min
SCLK low time
t4
10
ns min
SYNC to SCLK falling edge setup time
t5
3
ns min
Data setup time
t6
2
ns min
Data hold time
t7
0
ns min
SCLK falling edge to SYNC rising edge
t8
12
ns min
Minimum SYNC high time
t9
9
ns min
SYNC rising edge to next SCLK fall ignore
1 All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
2 Maximum SCLK frequency is 30 MHz.
t4
t3
t2
t5
t7
t6
D0
D1
D2
D22
D23
SYNC
SCLK
04
76
6-
0
02
t9
t1
t8
D23
D22
DIN
Figure 2. Timing Diagram
相關(guān)PDF資料
PDF描述
V24A3V3H264BG CONVERTER MOD DC/DC 3.3V 264W
V24A12H400BL CONVERTER MOD DC/DC 12V 400W
LTC2624IGN#TR IC DAC 12BIT QUAD R-R OUT 16SSOP
LTC2751IUHF-12#PBF IC DAC 12BIT CUR OUT 38-QFN
LTC1454CS IC D/A CONV 12BIT R-R DUAL16SOIC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD5063BRMZ-REEL71 制造商:AD 制造商全稱:Analog Devices 功能描述:Fully Accurate 16-Bit VOUT nanoDAC SPI Interface 2.7 V to 5.5 V in an MSOP
AD5064 制造商:AD 制造商全稱:Analog Devices 功能描述:Industrial Current/Voltage Output Driver
AD50641 制造商:AD 制造商全稱:Analog Devices 功能描述:Fully Accurate, 16-Bit, Unbuffered VOUT, Quad SPI Interface, 2.7 V to 5.5 V nanoDAC in a TSSOP
AD50643-2 制造商:Rochester Electronics LLC 功能描述:- Bulk
AD50647-4 制造商:Rochester Electronics LLC 功能描述:- Bulk