VOUT
參數(shù)資料
型號: AD5063BRMZ-1-REEL7
廠商: Analog Devices Inc
文件頁數(shù): 18/20頁
文件大?。?/td> 0K
描述: IC DAC 16BIT 2.7-5.5V 10MSOP
標(biāo)準(zhǔn)包裝: 1,000
系列: nanoDAC™
設(shè)置時間: 1µs
位數(shù): 16
數(shù)據(jù)接口: 串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 10-TFSOP,10-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 10-MSOP
包裝: 帶卷 (TR)
輸出數(shù)目和類型: 1 電壓,單極;1 電壓,雙極
采樣率(每秒): 333k
AD5063
Rev. C | Page 7 of
20
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AD5063
TOP VIEW
(Not to Scale)
VOUT
SYNC
110
AGND
SCLK
29
DIN
DACGND
38
04
766
-00
3
VREF
47
VDD
INV
RFB
56
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
DIN
Serial Data Input. This device has a 24-bit shift register. Data is clocked into the register on the falling edge of the
serial clock input.
2
VDD
Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and VDD should be decoupled to GND.
3
VREF
Reference Voltage Input.
4
VOUT
Analog Output Voltage from DAC.
5
INV
Connected to the Internal Scaling Resistors of the DAC. Connect the INV pin to the external op amp’s inverting
input in bipolar mode.
6
RFB
Feedback Resistor. In bipolar mode, connect this pin to the external op amp circuit.
7
AGND
Ground Reference Point for Analog Circuitry.
8
DACGND
Ground Input to the DAC.
9
SYNC
Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input data. When
SYNC goes low, it enables the input shift register, and data is then transferred in on the falling edges of the
following clocks. The DAC is updated following the 24th clock cycle unless SYNC is taken high before this edge, in
which case the rising edge of SYNC acts as an interrupt, and the write sequence is ignored by the DAC.
10
SCLK
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data
can be transferred at rates of up to 30 MHz.
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