VOUT
參數(shù)資料
型號(hào): AD5061BRJZ-1500RL7
廠商: Analog Devices Inc
文件頁數(shù): 18/20頁
文件大小: 0K
描述: IC DAC 16BIT SPI/SRL SOT23-8
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝: 500
系列: nanoDAC™
設(shè)置時(shí)間: 4µs
位數(shù): 16
數(shù)據(jù)接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 單電源
功率耗散(最大): 6mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: SOT-23-8
供應(yīng)商設(shè)備封裝: SOT-23-8
包裝: 帶卷 (TR)
輸出數(shù)目和類型: 1 電壓,單極;1 電壓,雙極
采樣率(每秒): 1.3M
AD5061
Rev. B | Page 7 of 20
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AD5061
TOP VIEW
(Not to Scale)
VOUT
SYNC
18
AGND
SCLK
27
DIN
DACGND
36
04
76
2-
0
03
VREF
45
VDD
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
DIN
Serial Data Input. This device has a 24-bit shift register. Data is clocked into the register on the falling edge of the
serial clock input.
2
VDD
Power Supply Input. These parts can be operated from 2.7 V to 5.5 V and VDD should be decoupled to GND.
3
VREF
Reference Voltage Input.
4
VOUT
Analog Output Voltage from DAC.
5
AGND
Ground Reference Point for Analog Circuitry.
6
DACGND
Ground Input to the DAC.
7
SYNC
Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input data. When SYNC
goes low, it enables the input shift register and data is transferred in on the falling edges of the following clocks.
The DAC is updated following the 24th clock cycle unless SYNC is taken high before this edge, in which case the
rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC.
8
SCLK
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can
be transferred at rates up to 30 MHz.
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