All input signals are specified with tR
參數(shù)資料
型號: AD5045BRUZ
廠商: Analog Devices Inc
文件頁數(shù): 24/28頁
文件大小: 0K
描述: IC DAC DUAL 14BIT SPI 14TSSOP
產(chǎn)品培訓模塊: Data Converter Fundamentals
DAC Architectures
標準包裝: 1
系列: nanoDAC™
設置時間: 5.8µs
位數(shù): 14
數(shù)據(jù)接口: 串行,SPI?
轉換器數(shù)目: 2
電壓電源: 單電源
功率耗散(最大): 13.5mW
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 14-TSSOP(0.173",4.40mm 寬)
供應商設備封裝: 14-TSSOP
包裝: 管件
輸出數(shù)目和類型: 2 電壓,單極;2 電壓,雙極
采樣率(每秒): *
AD5025/AD5045/AD5065
Rev. 0 | Page 5 of 28
TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 3 and
Figure 4. VDD = 4.5 V to 5.5 V. All specifications TMIN to TMAX, unless otherwise noted.
Table 4.
Parameter
Symbol
Min
Typ
Max
Unit
SCLK Cycle Time
20
ns
SCLK High Time
t2
10
ns
SCLK Low Time
t3
10
ns
SYNC to SCLK Falling Edge Setup Time
t4
16.5
ns
Data Setup Time
t5
5
ns
Data Hold Time
t6
5
ns
SCLK Falling Edge to SYNC Rising Edge
t7
0
30
ns
Minimum SYNC High Time (Single Channel Update)
t8
2
μs
Minimum SYNC High Time (All Channel Update)
t8
4
μs
SYNC Rising Edge to SCLK Fall Ignore
t9
17
ns
LDAC Pulse Width Low
t10
20
ns
SCLK Falling Edge to LDAC Rising Edge
t11
20
ns
CLR Pulse Width Low
t12
10
ns
SCLK Falling Edge to LDAC Falling Edge
t13
10
ns
CLR Pulse Activation Time
t14
10.6
μs
SCLK Rising Edge to SDO Valid
22
ns
SCLK Falling Edge to SYNC Rising Edge
5
30
ns
SYNC Rising Edge to SCLK Rising Edge
8
ns
SYNC Rising Edge to LDAC/CLR/PDL Falling Edge (Single Channel Update)
2
μs
SYNC Rising Edge to LDAC/CLR/PDL Falling Edge (All Channel Update)
4
μs
PDL Minimum Pulse Width
t19
20
ns
1 Maximum SCLK frequency is 50 MHz at VDD = 4.5 V to 5.5 V. Guaranteed by design and characterization; not production tested.
2 Daisy-chain mode only.
3 Measured with the load circuit of Figure 2. t15 determines the maximum SCLK frequency in daisy-chain mode.
Circuit and Timing Diagrams
2mA
IOL
2mA
IOH
VOH (MIN) + VOL (MAX)
2
TO OUTPUT
PIN
CL
50pF
06
84
4-
00
2
Figure 2. Load Circuit for Digital Output (SDO) Timing Specifications
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參數(shù)描述
AD5045BRUZ-REEL7 功能描述:IC DAC DUAL 14BIT SPI 14TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉換器 系列:nanoDAC™ 標準包裝:47 系列:- 設置時間:2µs 位數(shù):14 數(shù)據(jù)接口:并聯(lián) 轉換器數(shù)目:1 電壓電源:單電源 功率耗散(最大):55µW 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP(0.209",5.30mm 寬) 供應商設備封裝:28-SSOP 包裝:管件 輸出數(shù)目和類型:1 電流,單極;1 電流,雙極 采樣率(每秒):*
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