參數(shù)資料
型號: AD2S1200YSTZ
廠商: Analog Devices Inc
文件頁數(shù): 8/24頁
文件大小: 0K
描述: IC CONV R/D 12-BIT W/OSC 44-LQFP
標(biāo)準(zhǔn)包裝: 1
類型: R/D 轉(zhuǎn)換器
分辨率(位): 12 b
數(shù)據(jù)接口: 串行,并聯(lián)
電壓電源: 模擬和數(shù)字
電源電壓: 5V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 44-LQFP
供應(yīng)商設(shè)備封裝: 44-LQFP(7x7)
包裝: 托盤
產(chǎn)品目錄頁面: 790 (CN2011-ZH PDF)
配用: EVAL-AD2S1200CBZ-ND - BOARD EVAL FOR AD2S1200
AD2S1200
Rev. 0 | Page 16 of 24
INCREMENTAL ENCODER OUTPUTS
The incremental encoder emulation outputs A, B, and NM are
free running and are always valid, providing that valid resolver
format input signals are applied to the converter.
The AD2S1200 emulates a 1024-line encoder. Relating this to
converter resolution means one revolution produces 1,024 A, B
pulses. A leads B for increasing angular rotation (i.e., clockwise
direction). The addition of the DIR output negates the need for
external A and B direction decode logic. The DIR output
indicates the direction of the input rotation and it is high for
increasing angular rotation. DIR can be considered as an
asynchronous output and can make multiple changes in state
between two consecutive LSB update cycles. This occurs when
the direction of rotation of the input changes but the magnitude
of the rotation is less than 1 LSB.
The north marker pulse is generated as the absolute angular
position passes through zero. The north marker pulse width is
set internally for 90° and is defined relative to the A cycle.
Figure 9 details the relationship between A, B, and NM.
04406-0-009
A
B
NM
Figure 9. A, B, and NM Timing for Clockwise Rotation
Unlike incremental encoders, the AD2S1200 encoder output is
not subject to error specifications such as cycle error, eccentric-
ity, pulse and state width errors, count density, and phase . The
maximum speed rating, n, of an encoder is calculated from its
maximum switching frequency, fMAX, and its pulses per revo-
lution (PPR).
PPR
f
n
MAX
×
=
60
The AD2S1200 A, B pulses are initiated from XTALOUT, which
has a frequency of 4.096 MHz. The equivalent encoder
switching frequency is
)
1
4
(
024
.
1
096
.
4
/
1
Pulse
Updates
MHz
=
×
At 12 bits, the PPR = 1,024. Therefore, the maximum speed, n,
of the AD2S1200 is
rpm
n
60000
024
,
1
000
,
024
,
1
60
=
×
=
To get a maximum speed of 60,000 rpm, an external crystal of
8.192 MHz has to be chosen in order to produce an internal
CLOCKOUT equal to 4.096 MHz.
This compares favorably with encoder specifications where fMAX
is specified from 20 kHz (photo diodes) to 125 kHz (laser
based) depending on the light system used. A 1,024 line laser-
based encoder will have a maximum speed of 7,300 rpm.
The inclusion of A, B outputs allows the AD2S1200 plus
resolver solution to replace optical encoders directly without the
need to change or upgrade existing application software.
ON-BOARD PROGRAMMABLE SINUSOIDAL
OSCILLATOR
An on-board oscillator provides the sinusoidal excitation signal
(EXC) to the resolver as well as its complemented signal (EXC).
The frequency of this reference signal is programmable to four
standard frequencies (10 kHz, 12 kHz, 15 kHz, or 20 kHz) using
the FS1 and FS2 pins (see Table 7). FS1 and FS2 have internal pull-
ups, so the default frequency is 10 kHz. The amplitude of this
signal is centered on 2.5 V and has an amplitude of 3.6 V p-p.
Table 7. Excitation Frequency Selection
Frequency Selection (kHz)
FS1
FS2
10
1
12
1
0
15
0
1
20
0
The reference output of the AD2S1200 will need an external
buffer amplifier to provide gain and the additional current to
drive a resolver. Refer to Figure 6 for a suggested buffer circuit.
The AD2S1200 also provides an internal synchronous reference
signal that is phase locked to its Sin and Cos inputs. Phase
errors between the resolver primary and secondary windings
could degrade the accuracy of the RDC and are compensated by
this synchronous reference signal. This also compensates the
phase shifts due to temperature and cabling and eliminates the
need of an external preset phase compensation circuits.
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