參數(shù)資料
型號： AD1981BLJST-REEL
廠商： ANALOG DEVICES INC
元件分類： 消費家電
英文描述： AC 97 SoundMAX Codec
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP48
封裝： MS-026BBC, LQFP-48
文件頁數(shù)： 24/32頁
文件大?。?/td> 326K
代理商： AD1981BLJST-REEL
AD1981BL
SPDIF CONTROL REGISTER
Index 0x3A
Rev. A | Page 24 of 32
Reg No.
0x3A
Register 0x3A is a read/write register that controls SPDIF functionality and manages bit fields propagated as channel status (or subframe in the V case). With the
exception of V, this register should be written to only when the SPDIF transmitter is disabled (SPDIF bit in Register 0x2A is 0). This ensures that control and status
information start up correctly at the beginning of SPDIF transmission.
Table 35.
Bit
Mnemonic
Function
PRO
Professional
1 = Professional use of channel status.
0 = Consumer.
AUD
Nonaudio
1 = Data is non-PCM format.
0 = Data is PCM format.
COPY
Copyright
1 = Copyright is asserted.
0 = Copyright is not asserted.
PRE
Pre-emphasis
1 = Filter pre-emphasis is 50 μs/15 μs.
0 = Pre-emphasis is none.
CC [6:0]
Category Code
Programmed according to IEC standards, or as appropriate.
L
Generation Level
Programmed according to IEC standards, or as appropriate.
SPSR [1:0]
SPDIF Transmit
Sample Rate
SPSR [1:0] = 01: Reserved.
SPSR [1:0] = 10: Transmit sample rate is 48 kHz (reset default).
SPSR [1:0] = 11: Not supported.
V
Validity
This bit affects the validity flag (Bit 28 transmitted in each SPDIF L/R subframe) and enables the SPDIF
transmitter to maintain connection during error or mute conditions.
V = 1: Each SPDIF subframe (L + R) has Bit 28 set to 1. This tags both samples as invalid.
V = 0: Each SPDIF subframe (L + R) has Bit 28 set to 0 for valid data and 1 for invalid data (error
condition).
When V = 0, asserting the VFORCE bit (D15) in Register 0x2A (Ext’d Audio Stat/Ctrl) forces the validity
flag low, marking both samples as valid.
Name
SPDIF Control
D15
V
D14
X
D13
SPSR1
D12
SPSR0
D11
L
D10
CC6
D9
CC5
D8
CC4
D7
CC3
D6
CC2
D5
CC1
D4
CC0
D3
PRE
D2
COPY
D1
AUD
D0
PRO
Default
0x2000
SPSR [1:0] = 00: Transmit sample rate is 44.1 kHz.
EQ CONTROL REGISTER
Index 0x60
Reg No.
0x60
Register 0x60 is a read/write register that controls the equalizer functionality and data setup. This register contains the biquad and coefficient address pointer, which
is used in conjunction with the EQ data register (0x78) to set up the equalizer coefficients. The reset default disables the equalizer function until the coefficients can be
properly set up by the software and sets the symmetry bit to allow equal coefficients for left and right channels.
All registers are not shown, and bits containing an X are assumed to be reserved.
Table 36.
Bit
Mnemonic
Function
BCA [5:0]
Biquad and Coefficient
Address Pointer
biquad 0 coef a1 BCA[5:0] = 011010
biquad 0 coef a2 BCA[5:0] = 011001
biquad 0 coef b1 BCA[5:0] = 011101
biquad 0 coef b2 BCA[5:0] = 011100
biquad 1 coef a0 BCA[5:0] = 100000
biquad 1 coef a1 BCA[5:0] = 011111
Name
EQ Ctrl
D15
EQM
D14
MAD LBEN
D13
X
D12
X
D11
X
D10
X
D9
X
D8
X
D7
SYM
D6
CHS
D5
BCA5
D4
BCA4
D3
BCA3
D2
BCA2
D1
BCA1
D0
BCA0
Default
0x8080
biquad 0 coef a0 BCA[5:0] = 011011
相關PDF資料
PDF描述
AD1981BLJSTZ AC 97 SoundMAX Codec
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AD1981BLJSTZ2 AC ’97 SoundMAX㈢ Codec
相關代理商/技術參數(shù)
參數(shù)描述
AD1981BLJSTZ 制造商:Analog Devices 功能描述:Audio Codec 4ADC / 2DAC 20-Bit 48-Pin LQFP 制造商:Analog Devices 功能描述:IC AUDIO CODEC
AD1981BLJSTZ2 制造商:AD 制造商全稱:Analog Devices 功能描述:AC ’97 SoundMAX㈢ Codec
AD1981BLJSTZ-REEL 制造商:Analog Devices 功能描述:Audio Codec 4ADC / 2DAC 20-Bit 48-Pin LQFP T/R
AD1981BLJSTZ-REEL2 制造商:AD 制造商全稱:Analog Devices 功能描述:AC ’97 SoundMAX㈢ Codec
AD1981BWBSTZ 制造商:Analog Devices 功能描述:
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