參數(shù)資料
型號(hào)： AD1970JSTZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 19/20頁(yè)
文件大?。?/td> 0K
描述： IC ENCODER BTSC W/CODEC 48-LQFP
產(chǎn)品變化通告： AD1970 Discontinuation 04/Apr/2012
標(biāo)準(zhǔn)包裝： 1
類(lèi)型： 音頻編碼器
應(yīng)用： 機(jī)頂盒，視頻播放器，錄音機(jī)
電壓 - 電源，模擬： 3 V ~ 3.6 V
電壓 - 電源，數(shù)字： 3 V ~ 3.6 V
安裝類(lèi)型： 表面貼裝
封裝/外殼： 48-LQFP
供應(yīng)商設(shè)備封裝： 48-LQFP（7x7）
包裝： 托盤(pán)
AD1970
Rev. 0 | Page 8 of 20
Pin No.
Pin Name
Input/Output
Description
18
VIN_IAMPR
IN
Negative input of internal op amp for right channel input amplifier.
19
CAPLP
I/O
ADC Filter Capacitor Connection (positive left-channel input to modulator). A 1 nF
capacitor should be placed between this pin and analog ground.
20
CAPLN
I/O
ADC Filter Capacitor Connection (negative left-channel input to modulator). A 1 nF
capacitor should be placed between this pin and analog ground.
21
CAPRP
I/O
ADC Filter Capacitor Connection (positive right-channel input to modulator). A 1 nF
capacitor should be placed between this pin and analog ground.
22
CAPRN
I/O
ADC Filter Capacitor Connection (negative right-channel input to modulator). A 1 nF
capacitor should be placed between this pin and analog ground.
23
PVDD
PLL Power. 3.3 V nominal. Bypass capacitors should be placed close to this pin and
connected directly to the PLL ground.
24
PLL_LF
PLL Loop Filter Connection.
25
PGND
PLL Ground. Connect to DGND.
26
VID_IN
IN
Composite Video Input. Composite video signal input to the sync separator. The sync
output is connected to a PLL that generates the clocks for the AD1970. This pin has an
input impedance of 2 k.
27
NC
No Connect.
28
PLL_MODE0
IN
PLL Mode Select Pin 0. The setting of these pins indicates the source and frequency of the
input clock to generate the internal MCLK for the AD1970.
29
PLL_MODE1
IN
PLL Mode Select Pin 1. The setting of these pins indicates the source and frequency of the
input clock to generate the internal MCLK for the AD1970.
30
MCLK
IN
Master Clock Input. This input is used to generate the internal master clock if it is not
derived from the composite video signal on VID_IN. The master clock frequency must be
either fs or 256 × fs, where fs is the input sampling frequency. The PLL_CTRLx pins should
be set to accept the appropriate MCLK input frequency.
31
VID_PRES
OUT
Video Present Flag. A high logic level on this pin indicates that a valid composite video
signal is present on the VID_IN pin. Open-drain output.
32
XOUT
OUT
Crystal Oscillator Output. This pin is the output of the on-board oscillator and should be
connected to one side of a crystal.
33
XIN
IN
Crystal Oscillator Input. This pin is the input to the on-board oscillator and should be
connected to one side of a crystal.
34
GPIO0
IN/OUT
General Purpose I/O 0. This pin can be set to be either a static input or output, with levels
and direction controlled through the I2C port.
35
GPIO1
IN/OUT
General Purpose I/O 1. This pin can be set to be either a static input or output, with levels
and direction controlled through the I2C port.
36
DGND
Digital Ground.
37
DVDD
Digital Power.
38
GPIO2
IN/OUT
General Purpose I/O 2. This pin can be set to be either a static input or output, with levels
and direction controlled through the I2C port.
39
GPIO3
IN/OUT
General Purpose I/O 3. This pin can be set to be either a static input or output, with levels
and direction controlled through the I2C port.
40
SDATA
IN/OUT
Serial Data Input/Output (Before BTSC Encoding). Digital input to the BTSC encoder or
output of the ADC. The serial format is selected by writing to Bits 3:2 of Control Register 1.
41
BCLK
IN/OUT
Bit Clock Input/Output. Serial bit clock for clocking in the serial data. The interpretation of
BCLK changes according to the serial mode, which is set by writing to the control
registers.
42
LRCLK
IN/OUT
Left/Right Clock Input/Output. Left/right clock for framing the serial input data. The
interpretation of the LRCLK changes according to the serial mode, set by writing to the
control registers.
43
DIG_IN_EN
IN
Digital Input Enable (active high).
44
SDA
IN/OUT
I2C Serial Data Input/Output.
45
SCL
IN
I2C Serial Clock Input.
46
ADR1
IN
I2C Address 1. The address of the I2C port is set by these pins according to Table 16.
47
ADR0
IN
I2C Address 0. The address of the I2C port is set by these pins according to Table 16.
48
DGND
Digital Ground.
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