- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄8648 > AD1953YSTZRL (Analog Devices Inc)IC DSP DAC AUDIO3CH/26BIT 48LQFP PDF資料下載
參數(shù)資料
| 型號： | AD1953YSTZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 20/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP DAC AUDIO3CH/26BIT 48LQFP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準包裝： | 2,000 |
| 系列： | SigmaDSP® |
| 位數(shù)： | 26 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 3 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 540mW |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 6 電壓，單極 |
| 采樣率（每秒）： | 48k |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁當(dāng)前第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁
REV. 0
AD1953
–27–
Table XVI. Data Capture Register Write Format
Byte 0
Byte 1
Byte 2
Byte 3
00000, R/Wb, Adr[9:8]
Adr[7:0]
00000, ProgCount[8:6]
1
ProgCount[5:0], RegSel[1:0]
1, 2
NOTES
1. ProgCount[8:0] = value of program counter where trap occurs (see Table XXI).
2. RegSel[1:0] selects one of four registers (see Data Capture Register section).
Table XVII. Data_Capture_Serial Out Register (Address and Register Select) Write Format
Byte 0
Byte 1
Byte 2
Byte 3
00000, R/Wb, Adr[9:8]
Adr[7:0]
00000, ProgCount[8:6]
1
ProgCount[5:0], RegSel[1:0]
1, 2
NOTES
1. ProgCount[8:0] = value of program counter where trap occurs (see Table XXI).
2. RegSel[1:0] selects one of four registers (see Data Capture Registers section).
Table XVIII. Data Capture Read Format
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
00000, R/Wb, Adr[9:8]
Adr[7:0]
00000000
Data[23:16]
Data[15:8]
Data[7:0]
Table XIX. Safeload Register Write Format
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
00000, R/Wb, Adr[9:8]
Adr[7:0]
ParamAdr[7:0]
00, Param[21:16]
Param[15:8]
Param[7:0]
INITIALIZATION
Power-Up Sequence
The AD1953 has a built-in power-up sequence that initializes
the contents of all internal RAMs. During this time, the contents
of the internal program boot ROM are copied to the internal
program RAM, and likewise the SPI parameter RAM is filled
with values from its associated boot ROM. The data memories
are also cleared during this time.
The boot sequence lasts for 1024 MCLK cycles and starts on
the rising edge of the RESETB pin. Since the boot sequence
requires a stable master clock, the user should avoid writing to
or reading from the SPI registers during this period of time.
Note that the default power-on state of the internal clock mode
circuitry is 512
× f
S, or about 24 MHz for normal audio sample
rates. This mode bypasses all the internal clock doublers and
allows the external master clock to directly operate the DSP
core. If the external master clock is 256
× f
S, the boot sequence will
operate at this reduced clock rate and take slightly longer to
complete. After the boot sequence has finished, the clock modes
may be set via the SPI port. For example, if the external master
clock frequency is 256
× fS clock, the boot sequence would
take 1024 256
× f
S clock cycles to complete, after which an
SPI write could occur to put the AD1953 in 256
× f
S mode.
The default state of the MCLK input selector is MCLK0. Since
this input selector is controlled using the SPI port, and the SPI
port cannot be written to until the boot sequence is complete,
there must be a stable master clock signal present on the MCLK0
pin at startup.
Setting the Clock Mode
The AD1953 contains a clock doubler circuit that is used to
generate an internal 512
× f
S clock when the external clock is
256
× f
S. The clock mode is set by writing to Bit <2> of Control
Register 2.
When the clock mode is changed, it is possible that a glitch will
occur on the internal MCLK signal. This may cause the proces-
sor to inadvertently write an incorrect value into the data RAM,
which could cause an audio pop or click sound. To prevent this,
it is recommended that the following procedure be followed:
1. Assert the soft power-down bit (Bit <6> in Control Register 1)
to stop the internal MCLK.
2. Write the desired clock mode into Bit <2> of Control Register 2.
3. Wait at least 1 ms while the clock doublers settle.
4. Deassert the soft power-down bit.
An alternative procedure is to initiate a soft shutdown of the
processor core by writing a 1 to the halt program bit in Control
Register 1. This initiates a volume ramp-down sequence followed
by a shutdown of the DSP core. Once the core is shut down
(which can be verified by reading Bit <1> from Control Register 1,
or by waiting at least 20 ms), the new clock mode can be
programmed by writing to Bit <2> of Control Register 2. The
DSP core can then be restarted by clearing the halt program bit
in Control Register 1.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| VI-BNH-MV-B1 | CONVERTER MOD DC/DC 52V 150W |
| V375A36H400BF2 | CONVERTER MOD DC/DC 36V 400W |
| V375A2H160BL2 | CONVERTER MOD DC/DC 2V 160W |
| AD8802ARU | IC DAC 8BIT 12CH W/SD 20-TSSOP |
| VI-BNF-MV-B1 | CONVERTER MOD DC/DC 72V 150W |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD1953YSTZRL7 | 功能描述:IC DSP AUDIO 3CHAN 26BIT 48LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:SigmaDSP® 標(biāo)準包裝:47 系列:- 設(shè)置時間:2µs 位數(shù):14 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:55µW 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:管件 輸出數(shù)目和類型:1 電流，單極；1 電流，雙極 采樣率（每秒）:* |
| AD1954 | 制造商:AD 制造商全稱:Analog Devices 功能描述:SigmaDSP⑩ 3-Channel, 26-Bit Signal Processing DAC |
| AD1954YS | 制造商:Analog Devices 功能描述:DAC 3-CH Delta-Sigma 24-bit 44-Pin MQFP 制造商:Rochester Electronics LLC 功能描述:THREE CHANNEL, 24-BIT SIGMADSP DAC - Bulk |
| AD1954YSRL | 制造商:Analog Devices 功能描述:DAC 3-CH Delta-Sigma 24-bit 44-Pin MQFP T/R |
| AD1954YST | 制造商:Analog Devices 功能描述:DAC 3-CH Delta-Sigma 24-bit 48-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:THREE CHANNEL, 24-BIT SIGMADSP DAC - Tape and Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。