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參數(shù)資料
| 型號(hào)： | AD1928YSTZ-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 6/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CODEC 2ADC 8DAC W/PLL 48LQFP |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 類型： | 通用 |
| 數(shù)據(jù)接口： | 串行 |
| 分辨率（位）： | 24 b |
| ADC / DAC 數(shù)量： | 2 / 8 |
| 三角積分調(diào)變： | 是 |
| S/N 比，標(biāo)準(zhǔn) ADC / DAC (db)： | 94 / 94 |
| 動(dòng)態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db)： | 105 / 108 |
| 電壓 - 電源，模擬： | 3 V ~ 3.6 V |
| 電壓 - 電源，數(shù)字： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 帶卷 (TR) |
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AD1928
Rev. B | Page 14 of 32
ground connections with other unrelated digital output signals.
When the PLL is used, jitter in the reference clock is attenuated
above a certain frequency depending on the loop filter.
RESET AND POWER-DOWN
The function of the RST pin sets all the control registers to
their default settings. To avoid pops, reset does not power
down the analog outputs. After RST is deasserted and the PLL
acquires lock condition, an initialization routine runs inside the
AD1928. This initialization lasts for approximately 256 master
clock cycles.
The power-down bits in the PLL and Clock Control 0, DAC
Control 1, and ADC Control 1 registers power down the
respective sections. All other register settings are retained. The
reset pin, PD/RST, should be pulled low by an external resistor
to guarantee proper startup.
SERIAL CONTROL PORT
The AD1928 has an SPI control port that permits programming
and reading back of the internal control registers for the ADCs,
DACs, and clock system. There is also a standalone mode
available for operation without serial control that is configured
at reset using the serial control pins. All registers are set to
default, except the internal master clock enable is set to 1
and ADC BCLK and LRCLK master/slave is set by the COUT
pin. Standalone mode only supports stereo mode with an I2S
details. It is recommended to use a weak pull-up resistor on
CLATCH in applications that have a microcontroller. This pull-
up resistor ensures that the AD1928 recognizes the presence of
a microcontroller.
The SPI control port of the AD1928 is a 4-wire serial control
port. The format is similar to the Motorola SPI format, except
the input data-word is 24 bits wide. The serial bit clock and
latch can be completely asynchronous to the sample rate of the
ADCs and DACs. Figure 11 shows the format of the SPI signal.
The first byte is a global address with a read/write bit. For the
AD1928, the address is 0x04, shifted left 1 bit due to the R/W
bit. The second byte is the AD1928 register address and the
third byte is the data.
Table 11. Standalone Mode Selection
ADC Clocks
CIN
COUT
CCLK
CLATCH
Slave
0
Master
0
1
0
D0
D8
D22
D23
D9
CLATCH
CCLK
CIN
COUT
tCCH tCCL
tCDS tCDH
tCLS
tCCP
tCLH
tCOTS
tCOD
tCOE
06
62
3-
0
11
Figure 11. Format of SPI Signal
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