參數(shù)資料
型號: AD1877JRZ-RL
廠商: Analog Devices Inc
文件頁數(shù): 7/20頁
文件大?。?/td> 0K
描述: IC ADC STEREO 16BIT 28-SOIC
標準包裝: 1,000
位數(shù): 16
采樣率(每秒): 45k
數(shù)據(jù)接口: 串行
轉換器數(shù)目: 2
功率耗散(最大): 315mW
電壓電源: 模擬和數(shù)字
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 28-SOIC(0.295",7.50mm 寬)
供應商設備封裝: 28-SOIC W
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 2 個單端,單極
AD1877
REV. A
–15–
BCLK
RDEDGE = LO
BCLK
RDEDGE = HI
32
1
2
16
17
18
19
1
2
16
17
18
19
20
1
2
MSB-14
LSB
PREVIOUS DATA
MSB-1
LEFT DATA
MSB-2
LSB
RIGHT DATA
SOUT
OUTPUT
ZEROS
MSB-1 MSB-2
LSB
ZEROS
WCLK
OUTPUT
TAG
OUTPUT
MSB
LSB
LEFT TAG
MSB
LSB
RIGHT TAG
20
L
RCK
OUTPUT
MSB
Figure 12. Serial Data Output Timing. Master Mode, Right-Justified with MSB Delay,
WCLK Pulsed in 17th BCLK Cycle, S/
M = LO, RLJUST = Hl, MSBDLY = LO
BCLK
RDEDGE = LO
BCLK
RDEDGE = HI
31
32
1
2
3
16
SOUT
OUTPUT
WCLK
OUTPUT
TAG
OUTPUT
LSB
LEFT TAG
LSB
RIGHT TAG
31
32
1
2
3
16
MSB-1
LEFT DATA
MSB-2
LSB
MSB-1
RIGHT DATA
MSB-2
LSB
ZEROS
L
RCK
OUTPUT
17
18
17
18
MSB
Figure 13. Serial Data Output Timing: Master Mode, Left-Justified with No MSB Delay,
S/
M = LO, RLJUST = LO, MSBDLY = Hl
BCLK
RDEDGE = LO
BCLK
RDEDGE = HI
32
12
34
17
SOUT
OUTPUT
WCLK
OUTPUT
TAG
OUTPUT
MSB
LEFT TAG
MSB
RIGHT TAG
31
32
1
2
3
4
17
MSB-1
LEFT DATA
MSB-2
LSB
MSB-1
RIGHT DATA
MSB-2
LSB
ZEROS
OUTPUT
L
RCK
OUTPUT
MSB
LSB
MSB
LSB
Figure 14. Serial Data Output Timing: Master Mode, I2S-Justified, S/
M = LO, RLJUST = LO,
MSBDLY = LO
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