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參數(shù)資料
| 型號： | AD1859JRZ-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 7/16頁 |
| 文件大小： | 0K |
| 描述： | IC DAC STEREO SGL SUPP 5V 28SOIC |
| 產(chǎn)品培訓模塊： | Data Converter Fundamentals DAC Architectures |
| 產(chǎn)品變化通告： | AD1859 Discontinuation 12/Apr/2012 |
| 標準包裝： | 1 |
| 位數(shù)： | 18 |
| 數(shù)據(jù)接口： | DSP，I²S，串行，SPI? |
| 轉換器數(shù)目： | 2 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 330mW |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SOIC（0.295"，7.50mm 寬） |
| 供應商設備封裝： | 28-SOIC W |
| 包裝： | 標準包裝 |
| 輸出數(shù)目和類型： | 2 電壓，單極 |
| 采樣率（每秒）： | * |
| 其它名稱： | AD1859JRZ-RLDKR |
AD1859
REV. A
–15–
0
20k
2k
4k
6k
8k
10k
12k
14k
16k
18k
0
–10
–90
–50
–60
–70
–80
–30
–40
–20
–100
–110
–120
–130
–140
22k
10
0%
100
90
FREQUENCY – Hz
dBFS
Figure 30. 1 kHz Tone at –90 dBFS (16K-Point FFT) Includ-
ing Time Domain Plot Bandlimited to 22 kHz
0.0
3.5
0.5
1.0
1.5
2.0
2.5
3.0
0
–10
–90
–50
–60
–70
–80
–30
–40
–20
–100
–110
–120
–130
–140
–150
–160
dBFS
FS
Figure 31. Digital Filter Signal Transfer Function to
3.5
× F
S
Application Circuits
Figure 32 illustrates a 600 ohm line driver using the Analog
Devices SSM2017 and SSM2142 components. Figure 33
illustrates a “Numerically Controlled Oscillator” (NCO) that
can be implemented in programmable logic or a system ASIC to
provide the synchronous bit and left/right clocks from 27 MHz
for MPEG audio decoders. Note that the bit clock and left/right
clock outputs are highly jittered, but this jitter should be
perfectly acceptable. MPEG audio decoders are insensitive to
this clock jitter (using these signals to clock audio data from their
output serial port, and perhaps to decrement their audio/video
synchronization timer), while the AD1859 will reject the left/right
clock jitter by virtue of its on-chip digital phase locked loop.
Contact Analog Devices Computer Products Division Customer
Support at (617) 461-3881 or cpd_support@analog.com for more
information on this NCO circuit.
BCLK
LRCLK
SDATA
IDPM1
IDPM0
18/16
CLATCH
CDATA
CCLK
PD/RST
DEEMP
MUTE
XTALI/MCLK
XTALO
FGND
FILT
CMOUT
EMPR
OUTR
EMPL
OUTL
DVDD
AVDD
DGND
AGND
14
13
12
10
9
8
21
20
19
11
2
7
16
15
4
3
25
26
1
28
27
3
1
8
2
3
1
8
2
7
6
5
4
5
4
U2
SSM2017P
U3
SSM2017P
+15V
–15V
+15V
–15V
1Vrms
OUT
REF
V+
V–
V+
V–
VREF 2.25V
+5V
CC
+5V
DD
17
23
18
6
R2, 2k49
R1, 2k49
C8
100n
C1
100n
C9
100n
+
–
C10
C7
100n
C6
100n
C12
100n
C11
100n
AD1859-JR
GND
VIN
+V
–V
+OUT
+SENSE
–SENSE
–OUT
U4
SSM2142P
6
+15V
C5
100n
–15V
C4
100n
4
3
5
8
7
2
1
GND
VIN
+V
–V
+OUT
+SENSE
U5
SSM2142P
6
+15V
C3
100n
–15V
C2
100n
4
3
5
8
7
2
1
5Vrms
1
2
3
4
5
1
2
3
4
5
J1
P1
1
2
3
4
5
1
2
3
4
5
P2
J2
R3
600
R4
600
MAX OUTPUT EACH
CHANNEL
10Vrms (166.7mV V = +22dBm)
INTO 600
–SENSE
–OUT
+IN
RG1
RG2
–IN
47
+IN
RG1
RG2
–IN
Figure 32. 600 Ohm Balanced Line Driver
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