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參數(shù)資料
| 型號： | AD1851RZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 10/12頁 |
| 文件大小： | 0K |
| 描述： | IC DAC AUDIO FASTSET 16B 16SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 設(shè)置時(shí)間： | 1.5µs |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 雙 ± |
| 工作溫度： | -25°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC W |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 輸出數(shù)目和類型： | 2 電流，雙極；2 電壓，雙極 |
| 采樣率（每秒）： | 12.5M |
| 其它名稱： | AD1851RZ-REEL7DKR |
AD1851/AD1861
REV. A
–7–
AD1851 DIGITAL CIRCUIT CONSIDERATIONS
AD1851 Input Data
Data is transmitted to the AD1851 in a bit stream composed of
16-bit words with a serial, MSB first format. Three signals
must be present to achieve proper operation. They are the
Data, Clock and Latch Enable (LE) signals. Input data bits are
clocked into the input register on the rising edge of the Clock
signal. The LSB is clocked in on the 16th clock pulse. When all
data bits are loaded, a low-going Latch Enable pulse updates
the DAC input. Figure 5 illustrates the general signal require-
ments for data transfer to the AD1851.
DATA
CLOCK
LATCH
S
M
B
L
S
B
Figure 5. Signal Requirements for AD1851
Figure 6 illustrates the specific timing requirements that must
be met in order for the data transfer to be accomplished prop-
erly. The input pins of the AD1851 are both TTL and 5 V
CMOS compatible. The input requirements illustrated in Fig-
ures 5 and 6 are compatible with data outputs provided by
popular DSP filter chips used in digital audio playback systems.
The AD1851 input clock can run at a 12.5 MHz rate. This
clock rate will allow data transfer rates for 2 , 4
or 8
or
16
oversampling reconstructions.
>40ns
>30ns
>15ns
>40ns
DATA
CLOCK
LATCH
>15ns
>30ns
>80.0ns
>15ns
Figure 6. Timing Relationships of AD1851 Input Signals
AD1861 DIGITAL CIRCUIT CONSIDERATIONS
AD1861 Input Data
Data is transmitted to the AD1861 in a bit stream composed of
18-bit words with a serial, MSB first format. Three signals
must be present to achieve proper operation. They are the
Data, Clock and Latch Enable (LE) signals. Input data bits are
clocked into the input register on the rising edge of the Clock
signal. The LSB is clocked in on the 18th clock pulse. When all
data bits are loaded, a low-going Latch Enable pulse updates
the DAC input. Figure 7 illustrates the general signal require-
ments for data transfer to the AD1861.
DATA
CLOCK
LATCH
L
S
B
M
B
S
Figure 7. Signal Requirements for AD1861
Figure 8 illustrates the specific timing requirements that must
be met in order for the data transfer to be accomplished prop-
erly. The input pins of the AD1861 are both TTL and 5 V
CMOS compatible. The input requirements illustrated in Fig-
ures 7 and 8 are compatible with data outputs provided by
popular DSP filter chips used in digital audio playback systems.
The AD1861 input clock can run at a 13.5 MHz rate. This
clock rate will allow data transfer rates for 2 , 4
or 8
or
16
oversampling reconstructions.
>40ns
>30ns
>15ns
>40ns
DATA
CLOCK
LATCH
>15ns
>30ns
>74.1ns
>15ns
Figure 8. Timing Relationships of AD1861 Input Signals
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