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參數(shù)資料
| 型號： | AD1839AEB |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | Codec |
| 英文描述： | 2 ADC, 6 DAC, 96 kHz, 24-Bit Sigma-Delta Codec |
| 中文描述： | 2的ADC，6 DAC的，96千赫，24位Σ-Δ編解碼器 |
| 文件頁數(shù)： | 14/24頁 |
| 文件大?。?/td> | 674K |
| 代理商： | AD1839AEB |
AD1839A
SERIAL DATA PORTS—DATA FORMAT
The ADC serial data output mode defaults to the popular I
2
S
format, where the data is delayed by 1 BCLK interval from the
edge of the LRCLK. By changing Bits 6 to 8 in ADC Control
Register 2, the serial mode can be changed to right-justified
(RJ), left-justified DSP (DSP), or left-justified (LJ). In the RJ
mode, it is necessary to set Bits 4 and 5 to define the width of
the data-word. The DAC serial data input mode defaults to I
2
S.
By changing Bits 5, 6, and 7 in DAC Control Register 1, the
mode can be changed to RJ, DSP, LJ, or Packed Mode 256. The
word width defaults to 24 bits but can be changed by
reprogramming Bits 3 and 4 in DAC Control Register 1.
Rev. B | Page 14 of 24
PACKED MODES
The AD1839A has a packed mode that allows a DSP or other
controller to write to all DACs and read all ADCs using one
input data pin and one output data pin. Packed Mode 256 refers
to the number of BCLKs in each frame. The LRCLK is low
while data from a left-channel DAC or ADC is on the data pin;
LRCLK is high while data from a right-channel DAC or ADC is
on the data pin. DAC data is applied on the DSDATA1 pin, and
ADC data is available on the ASDATA pin. Figure 19 to
Figure 24 show the timing for the packed mode. Packed mode is
available for 48 kHz and 96 kHz.
AUXILIARY TIME DIVISION MULTIPLEXING
(TDM) MODE
A special auxiliary mode is provided to allow three external
stereo ADCs and one external stereo DAC to be interfaced to
the AD1839A to provide 8-in/8-out operation. In addition, this
mode supports a glueless interface to a single SHARC DSP
serial port, allowing a SHARC DSP to access all eight channels
of analog I/O. In this special mode, many pins are redefined; see
Table 9 for a list of redefined pins.
The auxiliary and TDM interfaces are independently
configurable to operate as masters or slaves. When the auxiliary
interface is set as a master, by programming the auxiliary mode
bit in ADC Control Register 2, AUXLRCLK and AUXBCLK are
generated by the AD1839A. When the auxiliary interface is set
as a slave, AUXLRCLK and AUXBCLK need to be generated by
an external ADC, as shown in Figure 27.
The TDM interface can be set to operate as a master or slave by
connecting the M/S pin to DGND or ODVDD, respectively. In
master mode, the FSTDM and BCLK signals are outputs and are
generated by the AD1839A. In slave mode, the FSTDM and
BCLK are inputs and should be generated by the SHARC. Both
48 kHz and 96 kHz operations are available (based on a
12.288 MHz or 24.576 MHz MCLK) in this mode.
Table 9. Pin Function Changes in Auxiliary Mode
Pin Name
ASDATA (O)
DSDATA1 (I)
DSDATA2 (I)/AAUXDATA1 (I)
DSDATA3 (I)/AAUXDATA2 (I)
AAUXDATA3 (I)
ALRCLK (O)
ABCLK (O)
DLRCLK (I)/AUXLRCLK (I/O)
I
2
S Mode
I
2
S Data Out, Internal ADC
I
2
S Data In, Internal DAC1
I
2
S Data In, Internal DAC2
I
2
S Data In, Internal DAC3
Not Connected
LRCLK for ADC
BCLK for ADC
LRCLK In/Out Internal DACs
Auxiliary Mode
TDM Data Out to SHARC.
TDM Data In from SHARC.
AUX-I
2
S Data In 1 (from external ADC).
AUX-I
2
S Data In 2 (from external ADC).
AUX-I
2
S Data In 3 (from external ADC).
TDM Frame Sync Out to SHARC (FSTDM).
TDM BCLK Out to SHARC.
AUX LRCLK In/Out. Driven by external LRCLK from ADC in slave mode.
In master mode, driven by MCLK/512.
AUX BCLK In/Out. Driven by external BCLK from ADC in slave mode.
In master mode, driven by MCLK/8.
AUX-I
2
S Data Out (to external DAC).
DBCLK (I)/AUXBCLK (I/O)
BCLK In/Out Internal DACs
DAUXDATA (O)
Not Connected
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