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參數(shù)資料
| 型號(hào)： | AD1839A |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | Codec |
| 英文描述： | 2 ADC, 6 DAC, 96 kHz, 24-Bit Sigma-Delta Codec |
| 中文描述： | 2的ADC，6 DAC的，96千赫，24位Σ-Δ編解碼器 |
| 文件頁數(shù)： | 22/24頁 |
| 文件大小： | 674K |
| 代理商： | AD1839A |
AD1839A
Table 16. ADC Control 2
Address
15, 14, 13, 12
1101
Rev. B | Page 22 of 24
R/W
11
0
RES
10
0
Function
ADC Data-
Word Width
Master/Slave Aux Mode
9
0 = Slave
1 = Master
ADC Data Format
8, 7, 6
000 = I
2
S
001 = RJ
010 = DSP
011 = LJ
100 = Packed 256
101 = Packed 128
110 = Auxiliary 256
111 = Auxiliary 512
AUXDATA
3
0 = Off
1 = On
RES
2
0
ADC MUTE
Right
1
0 = On
1 = Mute
Left
0
0 = On
1 = Mute
5, 4
00 = 24 Bits
01 = 20 Bits
10 = 16 Bits
11 = Reserved
Table 17. ADC Control 3
Address
R/W RES
15, 14,
13, 12
1110
0
RES
10
Reserved
9, 8
Function
IMCLK Clocking Scaling
7, 6
ADC Peak Readback
5
DAC Test Mode
4, 3, 2
ADC Test Mode
1, 0
11
0
0, 0
00 = MCLK × 2
01 = MCLK
10 = MCLK × 2/3
11 = MCLK × 2
0 = Disabled Peak Readback
1 = Enabled Peak Readback
000 = Normal Mode
All Others Reserved
00 = Normal Mode
All Others Reserved
CASCADE MODE
Dual AD1839A Cascade
The AD1839A can be cascaded to an additional AD1839A that,
in addition to six external stereo ADCs and two external stereo
DACs, can be used to create a 32-channel audio system with
16 inputs and 16 outputs. The cascade is designed to connect
to a SHARC DSP and operates in a time division multiplexing
(TDM) format. Figure 28 shows the connection diagram for
cascade operation. The digital interface for both parts must be
set to operate in Auxiliary 512 mode by programming ADC
Control Register 2. AD1839A Device 1 is set as the master
device by connecting the M/S pin to DGND; AD1839A
Device 2 is set as a slave device by connecting the M/S to
ODVDD. Both devices should be run from the same MCLK
and PD/RST signals to ensure that they are synchronized. With
Device 1 set as a master, it generates the frame-sync and bit
clock signals. These signals are sent to the SHARC and Device 2,
ensuring that both know when to send and receive data.
The cascade can be thought of as two 256-bit shift registers, one
for each device. At the beginning of a sample interval, the shift
registers contain the ADC results from the previous sample
interval. The first shift register (Device 1) clocks data into the
SHARC and clocks in data from the second shift register
(Device 2). While this is happening, the SHARC is sending DAC
data to the second shift register. By the end of the sample
interval, all 512 bits of ADC data in the shift registers have been
clocked into the SHARC and replaced by DAC data, which is
subsequently written to the DACs. Figure 29 shows the timing
diagram for the cascade operation.
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PDF描述 |
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| AD1839AAS | 2 ADC, 6 DAC, 96 kHz, 24-Bit Sigma-Delta Codec |
| AD1839AAS-REEL | 2 ADC, 6 DAC, 96 kHz, 24-Bit Sigma-Delta Codec |
| AD1839AASZ-REEL1 | 2 ADC, 6 DAC, 96 kHz, 24-Bit Sigma-Delta Codec |
| AD1839AASZ1 | 2 ADC, 6 DAC, 96 kHz, 24-Bit Sigma-Delta Codec |
| AD1839AEB | 2 ADC, 6 DAC, 96 kHz, 24-Bit Sigma-Delta Codec |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD1839AAS | 制造商:Analog Devices 功能描述:Audio Codec 2ADC / 6DAC 24-Bit 52-Pin MQFP 制造商:Rochester Electronics LLC 功能描述:HIGH PERFORMANCE CODEC I.C. - Bulk 制造商:Analog Devices 功能描述:IC CODEC SMD 1839 MQFP52 |
| AD1839AAS-REEL | 制造商:Analog Devices 功能描述:Audio Codec 2ADC / 6DAC 24-Bit 52-Pin MQFP T/R |
| AD1839AASZ | 制造商:Analog Devices 功能描述:Audio Codec 2ADC / 6DAC 24-Bit 52-Pin MQFP 制造商:Rochester Electronics LLC 功能描述:HIGH PERFORMANCE CODEC I.C. - Bulk |
| AD1839AASZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:2 ADC, 6 DAC, 96 kHz, 24-Bit Sigma-Delta Codec |
| AD1839AASZ-REEL | 制造商:Analog Devices 功能描述:Audio Codec 2ADC / 6DAC 24-Bit 52-Pin MQFP T/R |
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