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參數(shù)資料
| 型號(hào)： | AD1674KRZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 8/12頁(yè) |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT 100KSPS 28-SOIC |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 100k |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 825mW |
| 電壓電源： | 雙 ± |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SOIC W |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 2 個(gè)單端，單極；2 個(gè)單端，雙極 |
AD1674
REV. C
–5–
(for all grades TMIN to TMAX with VCC = +15 V
10% or +12 V
5%,
VLOGIC = +5 V
10%, VEE = –15 V
10% or –12 V
5%; VIL = 0.4 V,
VIH = 2.4 V unless otherwise noted)
SWITCHING SPECIFICATIONS
CONVERTER START TIMING (Figure 1)
J, K, A, B, Grades
T Grade
Parameter
Symbol Min Typ
Max
Min Typ Max Units
Conversion Time
8-Bit Cycle
tC
78
7
8
s
12-Bit Cycle
tC
910
9
10
s
STS Delay from CE
tDSC
200
225 ns
CE Pulse Width
tHEC
50
ns
CS
to CE Setup
tSSC
50
ns
CS
Low During CE High tHSC
50
ns
R/C to CE Setup
tSRC
50
ns
R/C Low During CE High tHRC
50
ns
A0 to CE Setup
tSAC
00
ns
A0 Valid During CE High tHAC
50
ns
READ TIMING—FULL CONTROL MODE (Figure 2)
J, K, A, B, Grades
T Grade
Parameter
Symbol Min
Typ
Max
Min Typ Max Units
Access Time
tDD
1
75
150
75
150 ns
Data Valid After CE Low
tHD
25
2
25
2
ns
20
3
15
4
ns
Output Float Delay
tHL
5
150
150 ns
CS
to CE Setup
tSSR
50
ns
R/C to CE Setup
tSRR
00
ns
A0 to CE Setup
tSAR
50
ns
CS
Valid After CE Low
tHSR
00
ns
R/C High After CE Low
tHRR
00
ns
A0 Valid After CE Low
tHAR
50
ns
NOTES
1t
DD is measured with the load circuit of Figure 3 and is defined as the time
required for an output to cross 0.4 V or 2.4 V.
20
°C to T
MAX.
3At –40
°C.
4At –55
°C.
5t
HL is defined as the time required for the data lines to change 0.5 V when
loaded with the circuit of Figure 3.
All min and max specifications are guaranteed.
Specifications subject to change without notice.
Test
VCP
COUT
Access Time High Z to Logic Low
5 V
100 pF
Float Time Logic High to High Z
0 V
10 pF
Access Time High Z to Logic High
0 V
100 pF
Float Time Logic Low to High Z
5 V
10 pF
t
HEC
CE
STS
DB11 – DB0
A0
CS
__
R/C
_
t
SSC
t
HSC
t
SRC
t
HRC
t
SAC
t
HAC
t
C
t
DSC
HIGH IMPEDANCE
Figure 1. Converter Start Timing
HIGH
IMPEDANCE
CE
STS
DB11 – DB0
A0
CS
__
R/C
_
t
HSR
t
SSR
t
HRR
t
SAR
t
HAR
t
DD
t
HL
HIGH
IMP.
DATA
VALID
t
HD
t
HS
t
SSR
Figure 2. Read Timing
VCP
DOUT
COUT
IOH
IOL
Figure 3. Load Circuit for Bus Timing Specifications
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