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參數(shù)資料
| 型號(hào)： | XC161CJ-16F |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 16-Bit Single-Chip Microcontroller with C166SV2 Core |
| 中文描述： | 16位單片機(jī)與C166SV2核心 |
| 文件頁數(shù)： | 70/87頁 |
| 文件大?。?/td> | 807K |
| 代理商： | XC161CJ-16F |
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XC161-16
Derivatives
Electrical Parameters
Data Sheet
68
V2.3, 2006-03
generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter
is negligible.
The value of the accumulated PLL jitter depends on the number of consecutive VCO
output cycles within the respective timeframe. The VCO output clock is divided by the
output prescaler (K = PLLODIV+1) to generate the master clock signal
f
MC
. Therefore,
the number of VCO cycles can be represented as K
×
N
, where
N
is the number of
consecutive
f
MC
cycles (TCM).
For a period of
N
×
TCM the accumulated PLL jitter is defined by the deviation D
N
:
D
N
[ns] =
±
(1.5 + 6.32
×
N
/
f
MC
);
f
MC
in [MHz],
N
= number of consecutive TCMs.
So, for a period of 3 TCMs @ 20 MHz and K = 12: D
3
=
±
(1.5 + 6.32
×
3
/ 20) = 2.448 ns.
This formula is applicable for K
×
N
< 95. For longer periods the K
×
N
= 95 value can be
used. This steady value can be approximated by: D
Nmax
[ns] =
±
(1.5 + 600 / (K
×
f
MC
)).
Figure 15
Approximated Accumulated PLL Jitter
Note: The bold lines indicate the minimum accumulated jitter which can be achieved by
selecting the maximum possible output prescaler factor K.
Different frequency bands can be selected for the VCO, so the operation of the PLL can
be adjusted to a wide range of input and output frequencies:
MCD05566
N
0
±1
±2
±3
±4
±5
±6
±7
±8
Acc. jitter
D
N
0
5
10
15
20
25
ns
K = 15
K = 12
K = 10
K = 8
K = 6 K = 5
1
10 MHz
20 MHz
40 MHz
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| XC161CJ-16F_06 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:16-Bit Single-Chip Microcontroller with C166SV2 Core |
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