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參數(shù)資料
| 型號： | AD1671S |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Complete 12-Bit 1.25 MSPS Monolithic A/D Converter |
| 中文描述： | 完整的12位125 MSPS的單片A / D轉(zhuǎn)換 |
| 文件頁數(shù)： | 12/16頁 |
| 文件大小： | 394K |
| 代理商： | AD1671S |
AD1671
REV. B
–12–
APPLICATIONS
AD1671 TO ADSP-2100A
Figure 16 demonstrates the AD1671 to ADSP-2100A interface.
The 2100A with a clock frequency of 12.5 MHz can execute an
instruction in one 80 ns cycle. The AD1671 is configured to
perform continuous time sampling. The DAV output of the
AD1671 is asserted at the end of each conversion. DAV can be
used to latch the conversion result into the two 574 octal
D-latches. The falling edge of the sampling clock is used to
generate an interrupt (IRQ3) for the processor. Upon interrupt,
the ADSP-2100A starts a data memory read by providing an
address on the DMA bus. The decoded address generates OE
for the latches and the processor reads their output over the
DMA bus. The conversion result is read within a single proces-
sor cycle.
+5V
ADSP-
2100A
DMA0:13
DMA0:15
DMACK
ADDRESS BUS
Q0:7
D0:7
574
OE
Q0:7
D0:7
574
D0:3
OE
DATA BUS
DAV
BIT1:12
ENCODE
16
8
4
8
4
DMRD
IRQ3
AD1671
SAMPLING
CLOCK
DECODE
8
Figure 16. AD1671 to ADSP-2100A Interface
AD1671 TO ADSP-2101/2102
Figure 17 is identical to the 2100A interface except the sam-
pling clock is used to generate an interrupt (IRQ2) for the pro-
cessor. Upon interrupt the ADSP-2100A starts a data memory
read by providing an address on the address (A) bus. The de-
code address generates OE for the D-latches and the processor
reads their output over the Data (D) bus. Reading the conver-
sion result is thus completed within a single processor cycle.
ADSP-2101
A0:13
D0:15
ADDRESS BUS
DECODE
Q0:7
D0:7
574
OE
Q0:7
D0:7
574
OE
DATA BUS
D0:3
16
8
4
8
8
4
RD
IRQ2
SAMPLING
CLOCK
DAV
BIT1:12
ENCODE
AD1671
Figure 17. AD1671 to ADSP-2101/ADSP-2102 Interface
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