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參數(shù)資料
| 型號： | AD1671JQ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | Complete 12-Bit 1.25 MSPS Monolithic A/D Converter |
| 中文描述： | 1-CH 12-BIT FLASH METHOD ADC, PARALLEL ACCESS, CDIP28 |
| 封裝： | CERDIP-28 |
| 文件頁數(shù)： | 9/16頁 |
| 文件大?。?/td> | 394K |
| 代理商： | AD1671JQ |
AD1671
REV. B
–9–
Table I is a list of grounding and decoupling rules that should
be reviewed before laying out a printed circuit board.
Table I. Grounding and Decoupling Guidelines
Power Supply
Decoupling
Comment
Capacitor Values
0.1
μ
F (Ceramic) and 1
μ
F
(Tantalum) Surface Mount Chip
Capacitors Recommended to
Reduce Lead Inductance
Directly at Positive and Negative
Supply Pins to Common Ground
Plane
Capacitor Locations
Reference (REF OUT)
Capacitor Value
1
μ
F (Tantalum) to ACOM
Grounding
Analog Ground
Ground Plane or Wide Ground
Return Connected to the Analog
Power Supply
Critical Common Connections
Should be Star Connected to REF
COM (as Shown in Figure 8)
Ground Plane or Wide Ground
Return Connected to the Digital
Power Supply
Connected Together Once at the
AD1671
Reference Ground
(REF COM)
Digital Ground
Analog and Digital Ground
UNIPOLAR (0 V TO +5 V) CALIBRATION
The AD1671 is factory trimmed to minimize offset, gain and
linearity errors. In some applications the offset and gain errors
of the AD1671 need to be externally adjusted to zero. This is
accomplished by trimming the voltage at AIN2 (Pin 22). The
circuit in Figure 9 is recommended for calibrating offset and
gain errors of the AD1671 when configured in the 0 V to +5 V
input range. If the offset trim resistor R1 is used, it should be
trimmed as follows, although a different offset can be set for a
particular system requirement. This circuit will give approxi-
mately
±
5 mV of offset trim range. Nominally the AD1671 is
intended to have a 1/2 LSB offset so that the exact analog input
for a given code will be in the middle of that code (halfway be-
tween the transitions to the codes above it and below it). Thus,
the first transition (from 0000 0000 0000 to 0000 0000 0001)
will occur for an input level of +1/2 LSB (0.61 mV for 5 V
range).
The gain trim is done by applying a signal 1 1/2 LSBs below the
nominal full scale (4.998 V for a 5 V range). Trim R2 to give
the last transition (1111 1111 1110 to 1111 1111 1111). This
circuit will give approximately
±
0.5% FS of adjustment range.
R2
50
ADJ
AIN1
AIN2
5k
5k
SHA OUT
BPO/UPO
AD1671
REF IN
REF OUT
SHA
1μF
50k
+5V
–5V
OFADJ
R1
25
0 TO +5V
V
IN
Figure 9. Unipolar (0 V to +5 V) Calibration
BIPOLAR (
6
5 V) CALIBRATION
The connections for the bipolar
±
5 V input range is shown in
Figure 10.
R2
50
ADJ
AIN1
AIN2
5k
5k
SHA OUT
BPO/UPO
AD1671
REF IN
REF OUT
SHA
1μF
50k
+5V
–5V
OFFADJ
R1
25
V
IN
–5V TO +5V
Figure 10. Bipolar (
±
5 V) Calibration
Bipolar calibration is similar to unipolar calibration. First, a sig-
nal 1/2 LSB above negative full scale (–4.9988 V) is applied and
R1 is trimmed to give the first transition (0000 0000 0000 to
0000 0000 0001). Then a signal 1 1/2 LSB below positive full
scale (+4.9963 V) is applied and R2 is trimmed to give the last
transition (1111 1111 1110 to 1111 1111
1111).
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| AD1671S | 制造商:AD 制造商全稱:Analog Devices 功能描述:Complete 12-Bit 1.25 MSPS Monolithic A/D Converter |
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