- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄375230 > AD1671J (Analog Devices, Inc.) Complete 12-Bit 1.25 MSPS Monolithic A/D Converter PDF資料下載
參數(shù)資料
| 型號： | AD1671J |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Complete 12-Bit 1.25 MSPS Monolithic A/D Converter |
| 中文描述： | 完整的12位125 MSPS的單片A / D轉(zhuǎn)換 |
| 文件頁數(shù)： | 10/16頁 |
| 文件大?。?/td> | 394K |
| 代理商： | AD1671J |
AD1671
REV. B
–10–
UNIPOLAR (0 V TO +2.5 V) CALIBRATION
The connections for the 0 V to +2.5 V input range calibration is
shown in Figure 11. Figure 11 shows an example of how the
offset error can be trimmed in front of the AD1671. The proce-
dure for trimming the offset and gain errors is the same as for
the unipolar 5 V range.
AIN1
AIN2
5k
5k
SHA OUT
BPO/UPO
AD1671
REF IN
REF OUT
SHA
OFFSET ADJ
+15V
1k
0 TO +2.5V
V
IN
10k
10k
R2
2k
ADJ
1μF
R1
1k
AD845
390
Figure 11. Unipolar (0 V to +2.5 V) Calibration
BIPOLAR (
6
2.5 V) CALIBRATION
The connections for the bipolar
±
2.5 V input range is shown in
Figure 12.
AIN1
AIN2
5k
5k
SHA OUT
BPO/UPO
AD1671
REF IN
REF OUT
SHA
OFFSET ADJ
+15V
1k
V
IN
10k
10k
R2
2k
ADJ
1μF
R1
1k
AD845
390
–2.5V TO +2.5V
Figure 12. Bipolar (
±
2.5 V) Calibration
OUTPUT LATCHES
Figure 13 shows the AD1671 connected to the 74HC574 octal
D-type edge-triggered latches with 3-state outputs. The latch
can drive highly capacitive loads (i.e., bus lines, I/O ports) while
maintaining the data signal integrity. The maximum setup and
hold times of the 574 type latch must be less than 20 ns (t
DD
and t
SS
minimum). To satisfy the requirements of the 574 type
latch the recommended logic families are S, AS, ALS, F or
BCT. New data from the AD1671 is latched on the rising edge
of the DAV (Pin 16) output pulse. Previous data can be latched
by inverting the DAV output with a 7404 type inverter.
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 8
DAV
BIT 9
BIT 10
BIT 11
BIT 12
DATA BUS
3-STATE
CONTROL
AD1671
1D
2D
3D
4D
5D
6D
7D
8D
CLOCK
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
OC
74HC574
1D
2D
3D
4D
5D
6D
7D
8D
CLOCK
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
OC
74HC574
Figure 13. AD1671 to Output Latches
OUT OF RANGE
An out-of-range condition exists when the analog input voltage
is beyond the input range (0 V to +2.5 V, 0 V to +5 V,
±
2.5 V,
±
5 V) of the converter OTR (Pin 15) is set low when the analog
input voltage is within the analog input range. OTR is set HIGH
and will remain HIGH when the analog input voltage exceeds
the input range by typically 1/2 LSB (OTR transition is tested to
±
6 LSBs of accuracy) from the center of the
±
full-scale output
codes. OTR will remain HIGH until the analog input is within
the input range and another conversion is completed. By logical
ANDing OTR with the MSB and its complement, overrange
high or underrange low conditions can be detected. Table II is a
truth table for the over/under range circuit in Figure 14. Sys-
tems requiring programmable gain conditioning prior to the
AD1671 can immediately detect an out-of-range condition, thus
eliminating gain selection iterations.
Table II. Out-of-Range Truth Table
OTR
MSB
Analog Input Is
0
0
1
1
0
1
0
1
In Range
In Range
Underrange
Overrange
MSB
OTR
MSB
OVER = "1"
UNDER = "1"
Figure 14. Overrange or Underrange Logic
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD1671JP | Complete 12-Bit 1.25 MSPS Monolithic A/D Converter |
| AD1671K | Complete 12-Bit 1.25 MSPS Monolithic A/D Converter |
| AD1671KP | ECONOLINE: RD & RC - Dual Output from a Single Input Rail- 1kVDC & 2kVDC Isolation- Power Sharing on Output- Custom Solutions Available- UL94V-0 Package Material- Efficiency to 86% |
| AD1671S | Complete 12-Bit 1.25 MSPS Monolithic A/D Converter |
| AD1671SQ | Complete 12-Bit 1.25 MSPS Monolithic A/D Converter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD1671JP | 功能描述:IC ADC SNGL 12BIT 28PLCC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標準包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應商設備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極 |
| AD1671JP-REEL | 制造商:Analog Devices 功能描述:ADC Single Pipelined 1.25Msps 12-bit Parallel 28-Pin PLCC T/R 制造商:Rochester Electronics LLC 功能描述:IC, 12-BIT 1.25 MSPS ADC - Tape and Reel |
| AD1671JPZ | 制造商:Analog Devices 功能描述:ADC Single Pipelined 1.25Msps 12-bit Parallel 28-Pin PLCC |
| AD1671JQ | 功能描述:IC ADC SNGL 12BIT 28-CDIP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:250 系列:- 位數(shù):12 采樣率（每秒）:1.8M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:1.82W 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-LQFP 供應商設備封裝:48-LQFP（7x7） 包裝:管件 輸入數(shù)目和類型:2 個單端，單極 |
| AD1671K | 制造商:AD 制造商全稱:Analog Devices 功能描述:Complete 12-Bit 1.25 MSPS Monolithic A/D Converter |
發(fā)布緊急采購，3分鐘左右您將得到回復。