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參數(shù)資料
| 型號： | AD1671AP |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | Complete 12-Bit 1.25 MSPS Monolithic A/D Converter |
| 中文描述： | 1-CH 12-BIT FLASH METHOD ADC, PARALLEL ACCESS, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁數(shù)： | 8/16頁 |
| 文件大?。?/td> | 394K |
| 代理商： | AD1671AP |
AD1671
REV. B
–8–
85
40
–50
0
50
45
–45
55
60
65
70
75
80
–5
–10
–15
–20
–25
–30
ANALOG INPUT – dB
–35
–40
S
Figure 7. Spurious Free Dynamic Range vs. Input
Amplitude, f
IN
= 250 kHz
APPLYING THE AD1671
GROUNDING AND DECOUPLING RULES
Proper grounding and decoupling should be a primary design
objective in any high speed, high resolution system. The
AD1671 separates analog and digital grounds to optimize the
management of analog and digital ground currents in a system.
The AD1671 is designed to minimize the current flowing from
REF COM (Pin 20) by directing the majority of the current
from V
CC
(+5 V–Pin 28) to V
EE
(–5 V–Pin 1). Minimizing ana-
log ground currents hence reduces the potential for large ground
voltage drops. This can be especially true in systems that do not
utilize ground planes or wide ground runs. REF COM is also
configured to be code independent, therefore reducing input de-
pendent analog ground voltage drops and errors. Code depen-
dent ground current is diverted to ACOM (Pin 27). Also critical
in any high speed digital design is the use of proper digital
grounding techniques to avoid potential CMOS “ground
bounce.” Figure 3 is provided to assist in the proper layout,
grounding and decoupling techniques.
AIN1
REF IN
BPO/UPO
ACOM
BIT 1
BIT 12
DCOM
AD1671
ENCODE
DAV
OTR
MSB
AGP*
DGP*
+5V
–5V
*GROUND PLANE RECOMMENDED
AIN2
REF OUT
SHA OUT
REF COM
1
μ
F
V
CC
V
EE
V
LOGIC
V (
±
5V)
1
18
28
+5V
0.1
μ
F
10
μ
F
23
22
20
27
19
25
26
24
21
13
2
17
16
15
14
0.1
μ
F
10
μ
F
0.1
μ
F
10
μ
F
Figure 8. AD1671 Grounding and Decoupling
Figure 4 plots both S/(N+D) and Effective Number of Bits
(ENOB) for a 100 kHz input signal sampled from 666 kHz to
1.25 MHz.
SAMPLING FREQUENCY – kHz
72.5
68
1250
68.5
70.5
714
666
69
69.5
70
71
71.5
72
1111
1000
909
833
769
S
11.75
11.50
11.25
11.00
E
Figure 4. S/(N/D) vs. Sampling Frequency, f
IN
= 100 kHz
Figure 5 is a THD plot for a full-scale 100 kHz input signal with
the sample frequency swept from 666 kHz to 1.25 MHz.
–68
–86
1250
–84
–76
714
666
–82
–80
–78
–74
–72
–70
1111
1000
909
833
769
SAMPLING FREQUENCY – kHz
T
Figure 5. THD vs. Sampling Rate, f
IN
= 100 kHz
The AD1671’s SFDR performance is ideal for use in communi-
cation systems such as high speed modems and digital radios.
The SFDR is better than 84 dB with sample rates up to 1.11 MHz
and increases as the input signal amplitude is attenuated by ap-
proximately 3 dB. Note also the SFDR is typically better than
80 dB with input signals attenuated by up to –7 dB.
1250
714
666
1111
1000
909
833
769
SAMPLING FREQUENCY – kHz
S
–86
–68
–70
–84
–76
–82
–80
–78
–74
–72
–88
–90
Figure 6. Spurious Free Dynamic Range vs. Sampling
Rate, f
IN
= 100 kHz
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| AD1671AQ | 制造商:Analog Devices 功能描述: |
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| AD1671JP-REEL | 制造商:Analog Devices 功能描述:ADC Single Pipelined 1.25Msps 12-bit Parallel 28-Pin PLCC T/R 制造商:Rochester Electronics LLC 功能描述:IC, 12-BIT 1.25 MSPS ADC - Tape and Reel |
| AD1671JPZ | 制造商:Analog Devices 功能描述:ADC Single Pipelined 1.25Msps 12-bit Parallel 28-Pin PLCC |
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