參數(shù)資料
型號(hào)： AD1555APZRL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 9/24頁(yè)
文件大?。?/td> 0K
描述： IC ADC PGA 24BIT LN 28-PLCC
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 24
采樣率（每秒）： 256k
數(shù)據(jù)接口： 串行，并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 96mW
電壓電源： 雙 ±
工作溫度： 0°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 28-LCC（J 形引線）
供應(yīng)商設(shè)備封裝： 28-PLCC（11.51x11.51）
包裝： 標(biāo)準(zhǔn)包裝
輸入數(shù)目和類(lèi)型： 1 個(gè)差分，雙極
其它名稱(chēng)： AD1555APZRLDKR
REV. B
AD1555/AD1556
–17–
external stresses such as lightning, the inputs AIN are specifi-
cally designed to ease the design. The external voltage spike
is generally clamped by devices T1 and T2 at about hundred
volts (for instance, devices T1 and T2 can be gas discharge
tubes) and then generates a pulsed current in the serial
resistances (R1, R3, and R2, R4). The AD1555 AIN inputs,
using robust internal clamping diodes to the analog supply
rails, can handle this huge pulsed input current (1.5 A during
2
s) without experiencing any destructive damages or
latch-up, whether or not the AD1555 is powered on. Mean-
while, enough time should be left between multiple spikes
to avoid excessive power dissipation.
Programming the AD1555
The different hardware events of the AD1555 as multiplexer
inputs selection, programmable gain settings, and power-down
modes are selectable using the control pins bus CB0 to CB4
according to the Table III. This table is only valid when MCLK
is toggling; otherwise, the AD1555 is powered down. When
used in combination with the AD1556, this control bus could
either be loaded by hardware (H/
S pin high) or via the serial
interface of the AD1556 (H/
S pin low).
The multiplexer, which exhibits a break-before-make switching
action, allows various combinations.
AIN (+)
AIN (–)
TIN (+)
TIN (–)
S1(+)
S1(–)
S2(+)
S2(–)
S3(+)
S3(–)
S4(+)
S4(–)
REFIN
REFCAP2
AGND3
22.5k
7.5k
500
AD1555
100
50
Figure 8. Simplified AD1555 Input Multiplexer
When the ground input is selected, S3(+) and S3(–) are closed,
all the other switches are opened, and the inputs of the pro-
grammable gain amplifier are shorted through an accurate
internal 1 k
resistor. This combination allows accurate calibra-
tion of the offset of the AD1555 for each gain setting. Also, a
system noise calibration can be done using the internal 1 k
resistor as a noise reference.
Table III. PGA Input and Gain Control
CB4
CB3
CB2
CB1
CB0
Description
00
0Ground Input with PGA Gain of 1
00
1Ground Input with PGA Gain of 2.5
00
01
0Ground Input with PGA Gain of 8.5
00
01
1Ground Input with PGA Gain of 34
00
10
0Ground Input with PGA Gain of 128
01
00
0Test Inputs TIN(+) and TIN(–) with PGA Gain of 1
01
00
1Test Inputs TIN(+) and TIN(–) with PGA Gain of 2.5
01
0Test Inputs TIN(+) and TIN(–) with PGA Gain of 8.5
01
1Test Inputs TIN(+) and TIN(–) with PGA Gain of 34
01
10
0Test Inputs TIN(+) and TIN(–) with PGA Gain of 128
10
00
0
Signal Inputs AIN(+) and AIN(–) with PGA Gain of 1
10
00
1
Signal Inputs AIN(+) and AIN(–) with PGA Gain of 2.5
10
01
0
Signal Inputs AIN(+) and AIN(–) with PGA Gain of 8.5
10
01
1
Signal Inputs AIN(+) and AIN(–) with PGA Gain of 34
10
0
Signal Inputs AIN(+) and AIN(–) with PGA Gain of 128
11
0
VREF Input with PGA Gain of 1
11
00
1
Sensor Test 1: Signal inputs AIN(+) and AIN(–) with
AIN(+) and AIN(–) inputs tied respectively to TIN(+)
and TIN(–) inputs and with PGA Gain of 1.
11
01
0
Sensor Test 2: Signal inputs TIN(+) and TIN(–) with
AIN(–) input tied to TIN(–) input and with PGA Gain of 1.
XX
10
1PGA Powered Down
XX
11
XChip Powered Down
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