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參數(shù)資料
| 型號： | AD1380KD |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | Low Cost 16-Bit Sampling ADC |
| 中文描述： | 2-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, CDIP32 |
| 封裝： | HERMETIC SEALED, BOTTOM BRAZED, CERAMIC, DIP-32 |
| 文件頁數(shù)： | 7/8頁 |
| 文件大?。?/td> | 240K |
| 代理商： | AD1380KD |
AD1380
–7–
REV. B
Figure 10. Analog and Power Connections for Bipolar –10 V
to +10 V Input Range
Other Ranges:
Representative digital coding for 0 V to +10 V
and –10 V to +10 V ranges is given above. Coding relationships
and calibration points for 0 V to +5 V, –2.5 V to +2.5 V and –
5 V to +5 V ranges can be found by halving proportionally the
corresponding code equivalents listed for the 0 V to +10 V and
–10 V to +10 V ranges, respectively, as indicated in Table II.
Zero and full-scale calibration can be accomplished to a preci-
sion of approximately
±
1/2 LSB using the static adjustment
procedure described above. By summing a small sine or triangu-
lar wave voltage with the signal applied to the analog input, the
output can be cycled through each of the calibration codes of
interest to more accurately determine the center (or end points)
of each discrete quantization level. A detailed description of this
dynamic calibration technique is presented in
Analog-Digital
Conversion Handbook,
edited by D. H. Sheingold, Prentice-Hall,
Inc., 1986.
GROUNDING, DECOUPLING AND LAYOUT
CONSIDERATIONS
Many data acquisition components have two or more ground
pins which are not connected together within the device. These
“grounds” are usually referred to as the Logic Power Return,
Analog Common (Analog Power Return) and Analog Signal
Ground. These grounds (Pins 8 and 30) must be tied together
at one point for the AD1380 as close as possible to the con-
verter. Ideally, a single, solid analog ground plane under the
converter would be desirable. Current flows through the wires
and etch stripes on the circuit cards, and since these paths have
resistance and inductance, hundreds of millivolts can be gener-
ated between the system analog ground point and the ground
pins of the AD1380. Separate wide conductor stripe ground
returns should be provided for high resolution converters to
minimize noise and IR losses from the current flow in the path
from the converter to the system ground point. In this way
AD1380 supply currents and other digital logic-gate return
currents are not summed into the same return path as analog
signals where they would cause measurement errors.
Each of the AD1380 supply terminals should be capacitively
decoupled as close to the AD1380 as possible. A large value
capacitor such as 1
μ
F in parallel with a 0.1
μ
F capacitor is
usually sufficient. Analog supplies are to be bypassed to the
Analog Power Return pin and the logic supply is bypassed to the
Logic Power Return pin.
The metal cover is internally grounded with respect to the
power supplies, grounds and electrical signals. Do not externally
ground the cover.
APPLICATION
AD1380 Dynamic Performance
High performance sampling analog-to-digital converters like the
AD1380 require dynamic characterization to assure they meet
or exceed their desired performance parameters for signal pro-
cessing applications. Key dynamic parameters include signal-to-
noise ratio (SNR) and total harmonic distortion (THD), which
are characterized using Fast Fourier Transform (FFT) analysis
techniques.
The results of that characterization are shown in Figure 11. In
the test a 13.2 kHz sine wave is applied as the analog input (f
O
)
at a level of l0 dB below full scale; the AD1380 is operated at a
word rate of 50 kHz (its maximum sampling frequency).
Figure 11.
The results of a 1024-point FFT demonstrate the exceptional
performance of the converter, particularly in terms of low noise
and harmonic distortion.
In Figure 11, the vertical scale is based on a full-scale input
referenced as 0 dB. In this way, all (frequency) energy cells can
be calculated with respect to full-scale rms inputs.
The resulting signal-to-noise ratio is 83.2 dB, which corresponds
to a noise floor of –93.2 dB.
Total harmonic distortion is calculated by adding the RMS
energy of the first four harmonics and equals –97.5 dB. Increas-
ing the input signal amplitude to –0.4 dB of full scale, causes
THD to increase to –80.6 dB as shown in Figure 12.
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