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| 型號： | AD1380JD |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | Low Cost 16-Bit Sampling ADC |
| 中文描述： | 2-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, CDIP32 |
| 封裝： | HERMETIC SEALED, BOTTOM BRAZED, CERAMIC, DIP-32 |
| 文件頁數(shù)： | 3/8頁 |
| 文件大?。?/td> | 240K |
| 代理商： | AD1380JD |
AD1380
–3–
REV. B
THEORY OF OPERATION
A 16-bit A/D converter partitions the range of analog inputs into
2
16
discrete ranges or quanta. All analog values within a given
quantum are represented by the same digital code, usually as-
signed to the nominal midrange value. There is an inherent
quantization uncertainty of
±
1/2 LSB, associated with the reso-
lution, in addition to the actual conversion errors.
The actual conversion errors that are associated with A/D con-
verters are combinations of analog errors due to the linear cir-
cuitry, matching and tracking properties of the ladder and
scaling networks, reference error and power supply rejection.
The matching and tracking errors in the converter have been
minimized by the use of monolithic DACs that include the
scaling network. The initial gain and offset errors are specified
at
±
0.1% FSR for gain and
±
0.05% FSR for offset. These errors
may be trimmed to zero by the use of external trim circuits as
shown in Figures 2 and 3. Linearity error is defined for unipolar
ranges as the deviation from a true straight line transfer charac-
teristic from a zero voltage analog input, which calls for a zero
digital output, to a point which is defined as a full scale. The
linearity error is based on the DAC resistor ratios. It is unadjust-
able and is the most meaningful indication of A/D converter
accuracy. Differential nonlinearity is a measure of the deviation
in the staircase step width between codes from the ideal least
significant bit step size (Figure 1).
Monotonic behavior requires that the differential linearity error
be less than 1 LSB; however, a monotonic converter can have
missing codes. The AD1380 is specified as having no missing
codes over temperature ranges as specified on the data page.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±
18 V
Logic Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . +7 V
Analog Ground to Digital Ground . . . . . . . . . . . . . . . .
±
0.3 V
Analog Inputs (Pins 6, 7, 31) . . . . . . . . . . . . . . . . . . . . . .
±
V
S
Digital Input . . . . . . . . . . . . . . . . . . . . –0.3 V to V
DD
+0.3 V
Output Short Circuit Duration to Ground
Sample/Hold . . . . . . . . . . . . . . . . . . . . . . . . . . . . Indefinite
Data . . . . . . . . . . . . . . . . . . . . . . 1 sec for Any One Output
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . +175
°
C
Storage Temperature . . . . . . . . . . . . . . . . . . –65
°
C to +150
°
C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . +300
°
C
ORDERING GUIDE
Max Linearity Temperature
Error
Model
Range
Package Option
AD1380JD
AD1380KD 0.003% FSR
0.006% FSR
0
°
C to +70
°
C
0
°
C to +70
°
C
Ceramic (DH-32E)
Ceramic (DH-32E)
There are three types of drift error over temperature: offset, gain
and linearity. Offset drift causes a shift of the transfer character-
istic left or right on the diagram over the operating temperature
range. Gain drift causes a rotation of the transfer characteristic
about the zero for unipolar ranges or minus full-scale point for
bipolar ranges. The worst case accuracy drift is the summation
of all three drift errors over temperature. Statistically, however,
the drift error behaves as the root-sum-squared (RSS) and can
be shown as:
RSS
=
∈
G
2
+ ∈
O
2
+ ∈
L
2
∈
G
= Gain Drift Error (ppm/
°
C)
∈
O
= 0ffset Drift Error (ppm of FSR/
°
C)
∈
L
= Linearity Error (ppm of FSR/
°
C)
Figure 1. Transfer Characteristics for an Ideal Bipolar A/D
DESCRIPTION OF OPERATION
On receipt of a CONVERT START command, the AD1380
converts the voltage at its analog input into an equivalent 16-bit
binary number. This conversion is accomplished as follows: the
16-bit successive approximation register (SAR) has its 16-bit
outputs connected to both the device bit output pins and the
corresponding bit inputs of the feedback DAC. The analog
input is successively compared to the feedback DAC output,
one bit at a time (MSB first, LSB last). The decision to keep
or reject each bit is then made at the completion of each bit
comparison period, depending on the state of the comparator
at that time.
WARNING!
ESD SENSITIVE DEVICE
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD1380 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
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