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參數(shù)資料
| 型號(hào)： | AD10677 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 16-Bit, 65 MSPS A/D Converter |
| 中文描述： | 16位65 MSPS A / D轉(zhuǎn)換 |
| 文件頁(yè)數(shù)： | 11/20頁(yè) |
| 文件大?。?/td> | 643K |
| 代理商： | AD10677 |
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AD10677
Rev. B | Page 11 of 20
FUNDAMENTAL LEVEL (dBFS)
d
–80
–70
–60
–50
–40
–30
–20
–10
0
0
10
20
30
40
50
60
70
80
90
100
SFDR 30MHz
SNR 30MHz
SFDR 10MHz
SNR 10MHz
SFDR 2.5MHz
SNR 2.5MHz
0
Figure 13. SFDR and SNR vs. Analog Input Level
ANALOG INPUT FREQUENCY (MHz)
d
76
78
80
82
84
86
88
90
92
94
96
SNR
SFDR
0
10
15
20
25
30
35
5
0
Figure 14. SFDR and SNR vs. Analog Input Frequency
DEFINITION OF SPECIFICATIONS
Analog Bandwidth
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
Aperture Delay
The delay between the 50% point on the rising edge of the
ENCODE command and the instant at which the analog input
is sampled.
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
Differential Nonlinearity
The deviation of any code from an ideal 1 LSB step.
Integral Nonlinearity
The deviation of the transfer function from a reference line
measured in fractions of 1 LSB using a best straight line
determined by a least square curve fit.
Encode Pulse Width/Duty Cycle
Pulse width high is the minimum amount of time the ENCODE
pulse should be left in a Logic 1 state to achieve rated
performance; pulse width low is the minimum time the
ENCODE pulse should be left in a low state. At a given clock
rate, these specifications define an acceptable encode duty cycle.
Harmonic Distortion
The ratio of the rms signal amplitude to the rms value of the
worst harmonic component.
Minimum Conversion Rate
The encode rate when the SNR of the lowest analog signal
frequency drops by3 dB or less below the guaranteed limit.
Maximum Conversion Rate
The encode rate at which parametric testing is performed.
Output Propagation Delay
The delay between the 50% point of the rising edge of the
ENCODE command and the time when all output data bits are
within valid logic levels.
Power Supply Rejection Ratio
The ratio of a change in output offset voltage to a change in
power supply voltage.
Signal-to-Noise-and-Distortion (SINAD)
The ratio of the rms signal amplitude (set at 1 dB below full
scale) to the rms value of the sum of all other spectral
components, including the first five harmonics and dc. May be
reported in dBc (i.e., degrades as signal levels is lowered) or in
dBFS (always related back to converter full scale).
Signal-to-Noise Ratio (SNR)
The ratio of the rms signal amplitude (set at 1 dB below full
scale) to the rms value of the sum of all other spectral
components, excluding the first five harmonics and dc. May be
reported in dBc (i.e., degrades as the signal level is lowered) or
in dBFS (always related back to converter full scale).
Spurious-Free Dynamic Range (SFDR)
The ratio of the rms signal amplitude to the rms value of the
peak spurious spectral component. The peak spurious
component may or may not be a harmonic. SFDR may be
reported in dBc (i.e., degrades as signal level is lowered) or in
dBFS (always related back to converter full scale).
Two-Tone Intermodulation Distortion Rejection (IMD)
The ratio of the rms value of an input tone to the rms value of
the worst third-order intermodulation product; reported in dBc.
Voltage Standing-Wave Ratio (VSWR)
The ratio of the amplitude of the elective field at a voltage
maximum to that at an adjacent voltage minimum.
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相關(guān)代理商/技術(shù)參數(shù) |
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| AD10677/PCB | 制造商:Analog Devices 功能描述:EVALUATION BOARD for AD10677 制造商:Analog Devices 功能描述:EVAL BD FOR AD10677 - Bulk |
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| AD10678/PCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:16-Bit, 80 MSPS A/D Converter |
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