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參數(shù)資料
| 型號： | AD10242/PCB |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 4/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | KIT EVAL PCB FOR AD10242 |
| 標準包裝： | 1 |
| ADC 的數(shù)量： | 2 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 40M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 輸入范圍： | ±2 V |
| 在以下條件下的電源（標準）： | 1.75W @ 40MSPS |
| 工作溫度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD10242 |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | AD10242BZ-ND - IC ADC DUAL 12BIT 68-CLCC |
AD10242
–12–
REV. C
USING THE FLEXIBLE INPUT
The AD10242 has been designed with the user’s ease of opera-
tion in mind. Multiple input configurations have been included on
board to allow the user a choice of input signal levels and input
impedance. While the standard inputs are
±0.5 V, ±1.0 V, and
±2.0 V, the user can select the input impedance of the AD10242
on any input by using the other inputs as alternate locations for
GND or an external resistor. The following chart summarizes the
impedance options available at each input location:
AIN1 = 100
when A
IN2 and AIN3 are open.
AIN1 = 75
when A
IN3 is shorted to GND.
AIN1 = 50
when AIN2 is shorted to GND.
AIN2 = 200
when A
IN3 is open.
AIN2 = 100
when A
IN3 is shorted to GND.
AIN2 = 75
when AIN2 to AIN3 has an external resistor of
AIN2 = 300
, with A
IN3 shorted to GND.
AIN2 = 50
when A
IN2 to AIN3 has an external resistor of AIN2
=
100
, with AIN3 shorted to GND.
AIN3 = 400
.
AIN3 = 100
when A
IN3 has an external resistor of 133
to GND.
AIN3 = 75
when AIN3 has an external resistor of 92 to GND.
AIN3 = 50
when A
IN3 has an external resistor of 57
to GND.
While the analog inputs of the AD10242 are designed for
dc- coupled bipolar inputs, the AD10242 has the ability to
use unipolar inputs in a user selectable mode through the addi-
tion of an external resistor. This allows for 1 V, 2 V, and 4 V
full-scale unipolar signals to be applied to the various inputs
(AIN1, AIN2, and AIN3, respectively). Placing a 2.43 k
resis-
tor (typical, offset calibration required) between UPOS and
UCOM shifts the reference voltage setpoint to allow a unipolar
positive voltage to be applied at the inputs of the device. To cali-
brate offset, apply a midscale dc voltage to the converter while
adjusting the unipolar resistor for a midscale output transition.
AIN2
UPOS
AD10242
2.43k
UCOM
AIN3
AIN1
Figure 13. Unipolar Positive
To operate with –1 V, –2 V, or –4 V full-scale unipolar signals,
place a 2.67 k
resistor (typical, offset calibration required)
between UNEG and UCOM. This again shifts the reference volt-
age setpoint to allow a unipolar negative voltage to be applied at
the inputs of the device. To calibrate offset, apply a midscale dc
voltage to the converter while adjusting the unipolar resistor for
a midscale output transition.
AIN2
UNEG
AD10242
2.67k
UCOM
AIN3
AIN1
Figure 14. Unipolar Negative
GROUNDING AND DECOUPLING
Analog and Digital Grounding
Proper grounding is essential in any high speed, high resolution
system. Multilayer printed circuit boards (PCBs) are recom-
mended to provide optimal grounding and power schemes. The
use of ground and power planes offers distinct advantages:
1. The minimization of the loop area encompassed by a signal
and its return path.
2. The minimization of the impedance associated with ground
and power paths.
3. The inherent distributed capacitor formed by the power
plane, PCB insulation, and ground plane.
These characteristics result in both a reduction of electro-
magnetic interference (EMI) and an overall improvement in
performance.
It is important to design a layout that prevents noise from cou-
pling to the input signal. Digital signals should not be run in
parallel with input signal traces and should be routed away from
the input circuitry. The AD10242 does not distinguish between
analog and digital ground pins as the AD10242 should always
be treated like an analog component. All ground pins should be
connected together directly under the AD10242. The PCB
should have a ground plane covering all unused portions of the
component side of the board to provide a low impedance path
and manage the power and ground currents. The ground plane
should be removed from the area near the input pins to reduce
stray capacitance.
LAYOUT INFORMATION
The schematic of the evaluation board (Figure 15) represents a
typical implementation of the AD10242. The pinout of the
AD10242 is very straightforward and facilitates ease of use
and the implementation of high frequency/high resolution
design practices. It is recommended that high quality ceramic
chip capacitors be used to decouple each supply pin to ground
directly at the device. All capacitors except the one placed on
ENCODE can be standard high quality ceramic chip capacitors.
The capacitor used on the
ENCODE pin must be a low induc-
tance chip capacitor as referenced previously.
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