參數(shù)資料
型號(hào): ACPL-W611-060
元件分類: 光電耦合器
英文描述: 1 CHANNEL LOGIC OUTPUT OPTOCOUPLER
文件頁數(shù): 8/10頁
文件大?。?/td> 91K
代理商: ACPL-W611-060
7
Switching Specifications (AC)
Over recommended operating conditions TA = -40°C to 85°C,VCC = 5 V, IF = 7.5 mA unless otherwise specified.
All typicals at VCC = 5 V,TA = 25 °C.
Parameter
Symbol
Min.
Typ.
Max.
Units
Test Conditions
Fig.
Note
Propagation Delay Time to
tPLH
20
48
75
ns
TA = 25°CRL = 350 ,5
High Output Level
100
CL = 15 pF
Propagation Delay Time to
tPHL
25
50
75
ns
TA = 25°C6
Low Output Level
100
Pulse Width Distortion
|tPHL - tPLH|3.5
35
ns
RL = 350 ,10
CL = 15 pF
Propagation Delay Skew
tPSK
40
ns
10, 11
Output Rise Time (10%-90%)
tR
24
ns
Output Fall Time (10%-90%)
tF
10
ns
Output High Level Common
|CMH|10
15
kV/
sV
CC = 5 V, IF = 0 mA,
Mode Transient Immunity
VO(MIN) = 2 V,
RL = 350 ,
TA = 25°C,
VCM = 1000 V
7, 9
Output Low Level Common
|CML|10
15
kV/
sV
CC = 5 V, IF = 7.5 mA,
8, 9
Mode Transient Immunity
VO(MAX) = 0.8 V,
RL = 350 ,
TA = 25°C,
VCM = 1000 V
Package Characteristics
All typicals at TA = 25 °C.
Parameter
Symbol
Min.
Typ.
Max.
Units
Test Conditions
Fig.
Note
Input-Output Insulation
VISO
3750
Vrms
RH < 50% for 1 min.
3, 4
TA = 25°C
Input-Output Resistance
RI-O
1012
VI-O = 500 V
3
Input-Output Capacitance
CI-O
0.6
pF
f = 1 MHz, TA = 25 °C3
Notes:
1.
Bypassing of the power supply line is required with a 0.1
F ceramic disc capacitor adjacent to each optocoupler.The total lead length
between both ends of the capacitor and the isolator pins should not exceed 10 mm.
2.
Peaking circuits may produce transient input currents up to 50 mA, 50 ns maximum pulse width, provided average current does not
exceed 20 mA.
3.
Device considered a two terminal device: pins 1, 2 and 3 shorted together, and pins 4, 5 and 6 shorted together.
4.
In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage
≥ 4500 V
RMS for 1 second (Leakage
detection current limit, II-O ≤ 5 A).
5.
The tPLH propagation delay is measured from 3.75 mA point on the falling edge of the input pulse to the 1.5 V point on the rising edge of
the output pulse.
6.
The tPHL propagation delay is measured from 3.75 mA point on the rising edge of the input pulse to the 1.5 V point on the falling edge of
the output pulse.
7.
CMH is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state
(i.e., VOUT > 2.0 V).
8.
CML is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state
(i.e., VOUT > 0.8 V).
9.
For sinusoidal voltages, (|dVCM|/dt)max = πfCMVCM(p-p).
10. See application section;“Propagation Delay, Pulse-Width Distortion and Propagation Delay Skew” for more information.
11. tPSK is equal to the worst case difference in tPHL and/or tPLH that will be seen between units at any given temperature within the worst
case operating condition range.
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