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參數(shù)資料
| 型號： | ACH16952DGG |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通用總線功能 |
| 英文描述： | JT 6C 6#20 SKT WALL RECP |
| 中文描述： | ALVC/VCX/A SERIES, DUAL 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56 |
| 封裝： | PLASTIC, TSSOP-56 |
| 文件頁數(shù)： | 9/12頁 |
| 文件大小： | 85K |
| 代理商： | ACH16952DGG |
Philips Semiconductors
Preliminary specification
74ALVCH16952
16-bit registered transceiver (3-State)
1998 Sep 01
9
AC WAVEFORMS
V
CC
= 2.3 TO 2.7 V RANGE
1. V
M
= 0.5 V
2. V
X
= V
OL
+ 0.15V
3. V
Y
= V
OH
– 0.15V
4. V
I
= V
5. V
OL
and V
OH
are the typical output voltage drop that occur with
the output load.
V
= 3.0 TO 3.6 V RANGE AND V
CC
= 2.7 V
1. V
M
= 1.5 V
2. V
X
= V
OL
+ 0.3V
3. V
Y
= V
OH
– 0.3V
4. V
I
= 2.7 V
5. V
OL
and V
OH
are the typical output voltage drop that occur with
the output load.
SY00030
CP
INPUT
V
M
t
PHL
t
PLH
V
OL
2.7V
V
M
GND
V
OH
An, Bn
OUTPUT
t
W
1/f
max
Waveform 1. Clock input (CP
BA
, CP
AB
) to output (Bn, An)
propagation delays, the clock pulse width and the maximum
clock pulse frequency.
ééé
ééé
ééé
éééééééé
éééééééé
éééééééé
t
h
t
h
V
M
An2.7V
CEnn
INPUT
GND
V
M
t
SU
NOTE:
The shaded areas indicate when the input is permitted to change
for predictable output performance.
SY00031
t
SU
2.7V
CP
INPUT
GND
Waveform 2. Set-up and hold times for the An, Bn and CE
XX
inputs.
t
PLZ
t
PZL
2.7V
OE
XX
INPUT
GND
V
CC
OUTPUT
LOW-to-OFF
OFF-to-LOW
V
OL
V
OH
OUTPUT
HIGH-to-OFF
OFF-to-HIGH
GND
outputs
enabled
outputs
enabled
outputs
disabled
t
PHZ
V
M
V
M
V
M
t
PZH
V
X
V
Y
SY00032
Waveform 3. 3-State enable and disable times
TEST CIRCUIT
PULSE
GENERATOR
R
T
V
IN
D.U.T.
V
OUT
C
L
V
CC
R
L
=500
SWITCH POSITION
TEST
t
PLH
/t
PHL
t
PLZ
/t
PZL
t
PHZ
/t
PZH
SWITCH
Open
2
V
CC
GND
Test Circuit for 3-State Outputs
Open
GND
S
1
2
V
CC
DEFINITIONS
R
L
= Load resistor
C
L
= Load capacitance includes jig and probe capacitance
R
T
=Termination resistance should be equal to Z
OUT
of pulse generators.
V
CC
2.7V
2.7 – 3.6V
V
IN
V
CC
2.7V
SW00047
R
L
=500
Load circuitry for switching times
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