參數(shù)資料
型號(hào): ACH16374DL
廠商: NXP SEMICONDUCTORS
元件分類: 通用總線功能
英文描述: JT 13C 13#22M SKT PLUG
中文描述: ALVC/VCX/A SERIES, DUAL 8-BIT DRIVER, TRUE OUTPUT, PDSO48
文件頁數(shù): 8/12頁
文件大?。?/td> 96K
代理商: ACH16374DL
Philips Semiconductors
Product specification
74ALVCH16374
16-bit edge-triggered D-type flip-flop (3-State)
1998 Jun 18
8
AC WAVEFORMS FOR V
CC
= 2.3V TO 2.7V AND
V
CC
< 2.3V RANGE
V
M
= 0.5 V
V
X
= V
OL
+ 0.15V
V
Y
= V
OH
–0.15V
V
OL
and V
OH
are the typical output voltage drop that occur with the
output load.
VI
= V
CC
AC WAVEFORMS FOR V
CC
= 3.0V TO 3.6V AND
V
CC
= 2.7V RANGE
V
M
= 1.5 V
V
X
= V
OL
+ 0.3V
V
Y
= V
–0.3V
V
and V
OH
are the typical output voltage drop that occur with the
output load.
VI
= 2.7V
V
M
V
M
1/f
MAX
t
w
t
PHL
t
PLH
CP INPUT
Qn OUTPUT
SW00078
GND
V
OH
V
OL
V
I
Waveform 1. Clock (CP) to output (Qn) propagation delays, the
clock pulse width and the maximum clock pulse frequency
t
PLZ
t
PZL
V
I
OE INPUT
GND
V
CC
OUTPUT
LOW-to-OFF
OFF-to-LOW
V
OL
V
OH
OUTPUT
HIGH-to-OFF
OFF-to-HIGH
GND
outputs
enabled
outputs
enabled
outputs
disabled
t
PHZ
V
M
V
M
V
M
t
PZH
V
X
V
Y
SW00072
V
M
Waveform 2. 3-State enable and disable times
V
M
SW00079
V
I
GND
éééé
éééé
éééé
ééééééé
ééééééé
ééééééé
V
M
Dn
INPUT
GND
V
M
V
OH
Qn
OUTPUT
V
OL
CP
INPUT
t
su
h
t
su
h
NOTE:
The shaded areas indicate when the input is permitted to change
for predictable output performance.
Waveform 3. Data set-up and hold times for the Dn input to the
CP input
TEST CIRCUIT
SWITCH POSITION
PULSE
GENERATOR
R
T
V
I
D.U.T.
V
O
C
L
V
CC
R
L
= 500
Test Circuit for switching times
Open
GND
S
1
DEFINITIONS
R
L
= Load resistor
C
L
= Load capacitance includes jig and probe capacitance
R
T
= Termination resistance should be equal to Z
OUT
of pulse generators.
V
CC
V
I
< 2.7V
V
CC
TEST
S
1
t
PLH/
t
PHL
Open
2
V
CC
t
PLZ/
t
PZL
2.7V
2.7–3.6V
t
PHZ/
t
PZH
GND
R
L
= 500
2 * V
CC
SV00906
Waveform 4. Load circuitry for switching times
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