參數(shù)資料
型號： ACE9050
廠商： Mitel Networks Corporation
英文描述： System Controller and Data Modem Advance Information
中文描述： 系統(tǒng)控制器和數(shù)據(jù)調(diào)制解調(diào)器進展信息
文件頁數(shù)： 18/52頁
文件大?。?/td> 390K
代理商： ACE9050
ACE9050
18
0000-001F
0020-007F
0080-17FF
1800-7FFF
8000-BFFF
C000-FDFF
FE00-FFFF
6303 Registers
Internal ACE9050 Registers
RAM
Non Banked external ROM
Banked external ROM
Non-Banked external ROM
Internal / External ROM
Table 23
Address (hex)
Description
External Pins
OEN
Output Enable, active low (pin 26)
This signal is used when accessing external memory or other
suitable devices. Driving the Output Enable input of external
memory reduces the possibility of data bus contention conditions.
WEN
Write Enable, active low (pin 27)
This output is used to latch data into external memory or other
suitable devices.
Associated Registers
IROM
Port 4 bit 1
The ACE9050 internal ROM (IROM) is mapped to the top 512
bytes of the address space allowing it to provide interrupt handler
routines. Upon reset the IROM select is enabled. It can and
should be disabled by software before the interrupts are enabled.
IROM
Address range FE00
H
-FFFF
H
:
0 = External ROM
1 = Internal ROM (reset state)
Bit 1
Description
Table 24
SLEEP
Port 3 Bit 1
If this bit is enabled then the CSEPN will become inactive
during periods when the 6303 is in Sleep mode. When the 6303
Sleep mode is activated, the processor puts FFFF
on the
address bus. The Decoder simply does not activate CSEPN for
this address when the SLEEP bit is enabled.
SLEEP
Address FFFF
H
:
0 = CSEPN active
1 = CSEPN inactive
Bit 1
Description
Table 25
1
RESET
RELEASED
READ
DATA FROM
DTFG
WAIT
UP TO 2 SEC
FOR 0A
OR 0B
NO
LOAD EITHER
MOTOROLA S-FORMAT
OR BINARY FILE CODE
INTO RAM AREA
FROM SCI
YES
PASS CONTROL
TO RAM PROGRAM
SET UP ACE9030
FOR 14·85MHz XTAL
SET UP ACE9030
FOR 15·36MHz XTAL
SET UP ACE9030
FOR 12·8MHz XTAL
PC TO 6303
RESET VECTOR
FFFE
ACE9050 RESET
IROM SELECTED
(PORT4 [1]–1)
START
IROM
CODE
FFFFFF
000000
0< DATA <FFFFFF
SERV
INPUT
0
SET UP SCI (UART):
9600 BAUD; 8 BIT: NO PARITY.
RECEIVE INTERRUPT
ENABLED
END FILE
INTERRUPT
VECTOR TABLE
RESET
TRAP
NI *
SWI
IRQ
ICF
OCF
TOF
SCI
0FFE
0FEE
0FFC
0FFA
0FF8
0FF6
0FF4
0FF2
0FF0
JUMP TO 1800
(START OF EXT ROM)
MAIN PROGRAM
IN
EXTERNAL ROM
RESET PORT4 [1]
* NI = NOT IMPLEMENTED
Fig. 12 Data flow for the internal ROM
4. BUS INTERFACE AND MEMORY BANKING
The Bus interface logic is responsible for the following:
1. External Interface to ACE9050 Data and Address buses
2. Creating 2 chip selects for external memory parallel devices.
3. The logic for the external banked addressing
4. Emulation Mode: External control of internal buses
Fig. 13 is the block diagram of the circuit. The ACE9050
memory interface can operate at a lower supply voltage than the
rest of the chip. This allows the use of low voltage memory parts.
The memory interface pads use a separate supply rail, which is
connected to V
DDM
.
External Pins
EMUL
Emulation mode (pin 83)
This input changes the function of the external data and address
buses. In Emulation mode (EMUL = 1), the internal Address and
Data buses are constructed from external stimuli and not the
internal 6303.
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