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參數(shù)資料
| 型號： | ACE9050 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | System Controller and Data Modem(為蜂窩式手機提供控制和邏輯接口功能的系統(tǒng)控制器和數(shù)據(jù)調(diào)制解調(diào)器) |
| 中文描述： | 系統(tǒng)控制器和數(shù)據(jù)調(diào)制解調(diào)器（為蜂窩式手機提供控制和邏輯接口功能的系統(tǒng)控制器和數(shù)據(jù)調(diào)制解調(diào)器） |
| 文件頁數(shù)： | 17/52頁 |
| 文件大小： | 366K |
| 代理商： | ACE9050 |
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ACE9050
17
6. Pass control to Program loaded in RAM
7. Map Interrupt Vectors to RAM space.
8. The RAM program can then Program a FLASH memory via
the UART.
Steps 1and 2 - Both Modes
The ACE Chipset offers the flexibility of using one of three
different crystal frequencies: 12·8, 14·85 or 15·36 MHz. The
chosen crystal can be used to generate all the system clocks and
local oscillator frequencies required n a cellular phone application.
The ACE9050 must detect what crystal is being used and set up
the correct value for the OSC8 dividers in the ACE9030. This is
handled in the Internal ROM. Upon Reset the ACE9030 sets the
OSC8 for a 15·36 MHz Crystal, so the ACE9050 is not clocked
faster than 8·064 MHz.
The system designer must set up the DTFG input (the Radio
Serial Interface, pin 82), using an external resistor of approximately
10k
. The crystal frequency determines where the resistor is
terminated, as shown in Table 21. Upon reset the ACE9050
Internal ROM reads the DTFG input and programs the ACE9030
OSC8 accordingly.
where:
nn = Number of bytes ( xx
1
pp
1
dd
1
cc ) in record.
pppp = Load address
dd = data bytes, 1 to 16
xxxx = Name of proqram (ASCII coded)
eeee = Program entry address
cc = checksum calculated from [255
2
sum(pp)
1
sum (dd)
1
sum (xx)
1
sum (ee)
1
nn)] MOD 256
When the ‘s9’ is read in from the End of File Record, the code
will jump to the reset vector. This is mapped to 0FFE by the
IROM. The RAM program will then begin execution as for a reset.
The last 6 characters of the record file (nneeeecc) will be
received while the program is running.
(b) Binary dump file
This format is for the binary representation of the code, not a
proprietary binary format code. The start code for this format is
‘OB’ ASCII (ie 30
H
, 42
H
) . First two bytes are the start address
pointer.
The next two bytes are the end address pointer
1
1. The next
bytes are the data bytes. These are loaded consecutively from
the start to the end address. When the last data byte is received
the program counter will go to the loaded code start address
pointer.
Step7-Interrupt Vector table
The Internal ROM will map the 6303 Interrupt vector table to
an address space in RAM so the loaded program can deal with
interrupts as shown in Table 22. In general only the SCI interrupt
is required for a Flash Loading program.
0FFE
0FEE
0FFC
0FFA
0FF8
0FF6
0FF4
0FF2
0FF0
Vector address
Interrupt
Reset
Trap
Not Implemented
SWI Software interrupt
IRQN
ICF Timer Input compare
OCF Timer Output compare
TOF Timer overflow
SCI
Table 22
RAM Area Reserved for IROM Operation
The IROM code itself requires a small amount of RAM during
its operation. This area must not be used for storage of the RAM
program.
RAM Reserved area: 080
to 100
Fig. 12 shows the data flow for the internal ROM.
3. DECODER
The Decoder logic creates the memory map for system
containing the ACE9050. Internally, it maps the ACE9050
registers, RAM and ROM onto the System Memory map. External
ROM is also mapped onto the available address space by the
Decoder, but the situation can be complicated by the Bank
Address switching circuitry. Refer to Table 23 on the following
page for details of memory mapping.
Note that the ACE9050 contains Memory Banked Switching
circuitry. Refer to the section 4 BUS INTERFACE AND MEMORY
BANKING’ below for details.
The Decoder also creates suitably timed Output Enable and
Write Enable signals (refer to Figs. 4 and 5) for parallel read and
write cycles to external devices.
Step 3 - Normal Mode
Program code in the external EPROM at address 1800
is
started. The Internal ROM resides at the top of the processor
address space FE00
- FFFF
. Obviously the main program
requires access to this space for Interrupt vectors. The Internal
ROM is deselected by setting PORT4 [1] to zero. It is
recommended that any external program does this quickly and
always before enabling any Interrupt sources.
Step 3 - Service Mode
The Internal ROM will initialise the 6303 SCI (UART) and set
up the Baud rate generator to 9600 Baud. The SCI is initialised
to the following:
Receiver On
Transmitter ON
Receive Interrupt enabled
9600 Baud rate from ACE9050 Baud Rate Generator
The Receive interrupt will remain enabled after the IROM code
execution. The UART is always configured for 8-bit data transfer,
no parity and one stop bit.
Steps 4, 5 and 6 - Service Mode
When in service mode the ACE9050 can download a program
from the SCI to RAM. To achieve this the first code (start code)
must be sent down to the SCI within 2 seconds of releasing
Reset. The boot block code will write the subsequent code into
RAM. Two code formats are supported:
(a) Motorola S- Record format
(b) Binary dump
(a) Motorola S-Record Format
The start code for this format is ‘OA’ in ASCII ( i.e. 30
H
, 41
H
).
s0nnppppxxxxxxxxxcc
s1nnppppdddddddddddddcc Data record with 16-bit address
·
s9nneeeecc
First Record in file
End of file record (nn = 3)
12·8MHz
14·85MHz
15·36MHz
Crystal
Serial Data RXed
000000
0 < Data < FFFFFF
FFFFFF
V
SS
(Gnd)
A1 (pin 31)
V
DD
Table 21
Resistor from
pin 82 to:
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| ACE9050 | System Controller and Data Modem Advance Information |
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| ACE9050C/IW/FP1N | 制造商:Microsemi Corporation 功能描述:PB FREE SYSTEM CONTROLLER & DATA MODEM - Bulk |
| ACE9050C/IW/FP1Q | 制造商:Microsemi Corporation 功能描述:PB FREE SYSTEM CONTROLLER & DATA MODEM - Bulk |
| ace9050c/iw/fp8q | 制造商:Rochester Electronics LLC 功能描述: 制造商:Zarlink Semiconductor Inc 功能描述: |
| ace9050d/ig/gp1n | 制造商:Microsemi Corporation 功能描述:CNTRLR AND DATA MODEM 100LQFP - Bulk 制造商:Rochester Electronics LLC 功能描述: 制造商:Zarlink Semiconductor Inc 功能描述: |
| ACE9050D/IG/GP2N | 制造商:Microsemi Corporation 功能描述:CNTRLR AND DATA MODEM 100LQFP - Bulk |
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