
2011 Microchip Technology Inc.
Preliminary
DS41569A-page 107
PIC16LF1904/6/7
TABLE 11-6:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
REGISTER 11-8:
ANSELB: PORTB ANALOG SELECT REGISTER
U-0
R/W-1/1
—
ANSB5
ANSB4
ANSB3
ANSB2
ANSB1
ANSB0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-6
Unimplemented:
Read as ‘0’
bit 5-0
ANSB<5:0>
: Analog Select between Analog or Digital Function on pins RB<5:0>, respectively
0
= Digital I/O. Pin is assigned to port or digital special function.
1
= Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
Note
1:
When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to allow external
control of the voltage on the pin.
REGISTER 11-9:
WPUB: WEAK PULL-UP PORTB REGISTER
R/W-1/1
WPUB7
WPUB6
WPUB5
WPUB4
WPUB3
WPUB2
WPUB1
WPUB0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
WPUB<7:0>
: Weak Pull-up Register bits
1
= Pull-up enabled
0
= Pull-up disabled
Note
1:
Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled.
2:
The weak pull-up device is automatically disabled if the pin is in configured as an output.
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
ANSELB
—
ANSB5
ANSB4
ANSB3
ANSB2
ANSB1
ANSB0
LATB
LATB7
LATB6
LATB5
LATB4
LATB3
LATB2
LATB1
LATB0
PORTB
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
WPUB
WPUB7
WPUB6
WPUB5
WPUB4
WPUB3
WPUB2
WPUB1
WPUB0
Legend:
x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by PORTB.