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參數資料
| 型號： | ABV8039QC-TFREQ |
| 廠商： | ABRACON CORP |
| 元件分類： | XO, clock |
| 英文描述： | VCXO, CLOCK, 38 MHz - CMOS OUTPUT |
| 封裝： | QFN |
| 文件頁數： | 3/10頁 |
| 文件大小： | 215K |
| 代理商： | ABV8039QC-TFREQ |
(Preliminary)
ABV8037/38/39
38MHz-320MHz Low Phase Noise VCXO
30332 Esperanza., Rancho Santa Margarita, Ca 92688 Ph: 949-546-8000 Fax: 949-546-8001 www.Abracon.com 9/1/05 Page 2
OUTPUT ENABLE LOGICAL LEVELS
Part #
OE
State
0 (Default)
Output enabled
ABV8038 (PECL)
1
Tri-state
0
Tri-state
ABV8037 & 39 (CMOS or CMOS)
1 (Default)
Output enabled
PIN DESCRIPTIONS
Name
TSSOP
Pin number
3x3mm QFN
Pin number
Type
Description
VDDANA
1
11
P
VDD for analog Circuitry.
XIN
2
12
I
Crystal input pin. (See Crystal Specifications on page 4).
XOUT
3
13
O
Crystal output pin. (See Crystal Specifications on page 4).
SEL2
4
14
I
Output frequency Selector pin.
OE_CTRL
5
15
I
Output enable control pin. (See OE_CTRL Logic Levels).
VCON
6
16
I
Voltage control input.
GNDANA
7
1
P
Ground for analog circuitry.
LP
8
2
-
LM
9
3
-
Tuning inductor connection. The inductor is recommended to be
a high Q small size 0402 or 0603 SMD component, and must be
placed between LP and adjacent LM pin. Place inductor as close
to the IC as possible to minimize parasitic effects and to
maintain inductor Q.
GNDBUF
10
4
P
GND connection for output buffer circuitry.
Q
11
5
O
PECL or LVDS output.
VDDBUF
12
6
P
VDD connection for output buffer circuitry. VDDBUF should be
separately decoupled from other VDDs whenever possible.
QBAR
13
7
O
Complementary PECL, LVDS, Or single ended CMOS output.
GNDBUF
14
8
P
GND connection for output buffer circuitry.
SEL1
15
9
I
Output frequency Selector pin.
SEL0
16
10
I
Output frequency Selector pin.
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| ABV8068 | 制造商:ABRACON 制造商全稱:Abracon Corporation 功能描述:320-640MHz Low Phase Noise VCXO |
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