參數(shù)資料
型號(hào)： AAT3218IJS-1.25-T1
廠商： Advanced Analog Technology,lnc.
英文描述： 150mA MicroPower⑩ High Performance LDO
中文描述： 150mA的微功耗高性能的LDO⑩
文件頁(yè)數(shù)： 14/18頁(yè)
文件大?。?/td> 384K
代理商： AAT3218IJS-1.25-T1
AAT3218
150mA MicroPower High Performance LDO
14
3218.2006.04.1.8
Figure 1: Common LDO Regulator Layout with C
BYP
Ripple Feedback Loop.
LDO
Regulator
C
BYP
C
OUT
R
TRACE
R
TRACE
R
TRACE
R
TRACE
C
IN
R
LOAD
VIN
EN
GND
VOUT
BYP
I
LOAD
I
RIPPLE
I
IN
V
IN
GND
DC INPUT
I
GND
C
BYP
GND
LOOP
I
LOAD
return + noise and ripple
I
BYP
+ noise
Figure 2 shows the preferred method for the bypass
and output capacitor connections. For low output
noise and highest possible power supply ripple
rejection performance, it is critical to connect the
bypass and output capacitor directly to the LDO reg-
ulator ground pin. This method will eliminate any
load noise or ripple current feedback through the
LDO regulator.
The power dissipation for a 150mA load occurring
for 8.2% of the duty cycle will be 21mW. Finally,
the two power dissipation levels can summed to
determine the total true power dissipation under
the varied load:
P
D(total)
= P
D(100mA)
+ P
D(150mA)
P
D(total)
= 156.6mW + 21mW
P
D(total)
= 177.6mW
The maximum power dissipation for the AAT3218
operating at an ambient temperature of 85°C is
211mW. The device in this example will have a total
power dissipation of 177.6mW. This is well within
the thermal limits for safe operation of the device.
Printed Circuit Board Layout
Recommendations
In order to obtain the maximum performance from
the AAT3218 LDO regulator, careful consideration
should be given to the printed circuit board (PCB)
layout. If grounding connections are not properly
made, power supply ripple rejection, low output self
noise, and transient response can be compromised.
Figure 1 shows a common LDO regulator layout
scheme. The LDO regulator, external capacitors
(C
IN
, C
OUT
, and C
BYP
), and the load circuit are all
connected to a common ground plane. This type of
layout will work in simple applications where good
power supply ripple rejection and low self noise are
not a design concern. For high-performance appli-
cations, this method is not recommended.
The problem with the layout in Figure 1 is the
bypass capacitor and output capacitor share the
same ground path to the LDO regulator ground pin,
along with the high-current return path from the
load back to the power supply. The bypass capac-
itor node is connected directly to the LDO regulator
internal reference, making this node very sensitive
to noise or ripple. The internal reference output is
fed into the error amplifier, thus any noise or ripple
from the bypass capacitor will be subsequently
amplified by the gain of the error amplifier. This
effect can increase noise seen on the LDO regula-
tor output, as well as reduce the maximum possi-
ble power supply ripple rejection. There is PCB
trace impedance between the bypass capacitor
connection to ground and the LDO regulator
ground connection. When the high load current
returns through this path, a small ripple voltage is
created, feeding into the C
BYP
loop.
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