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參數(shù)資料
| 型號： | A8450KLBTR-T |
| 廠商： | Allegro Microsystems Inc |
| 文件頁數(shù)： | 10/17頁 |
| 文件大小： | 546K |
| 描述： | IC REG QD BUCK/LINEAR 24-SOIC |
| 標準包裝： | 3,000 |
| 拓撲： | 降壓（降壓）（1），線性（LDO）（4） |
| 功能： | 車載 |
| 輸出數(shù)： | 4 |
| 電壓/電流 - 輸出 1： | 5.7V，1.2A |
| 電壓/電流 - 輸出 2： | 5V，200mA |
| 電壓/電流 - 輸出 3： | 5V，200mA |
| 帶 LED 驅(qū)動器： | 無 |
| 帶監(jiān)控器： | 無 |
| 帶序列發(fā)生器： | 是 |
| 電源電壓： | 6 V ~ 45 V |
| 工作溫度： | -40°C ~ 135°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-SOIC W |
| 包裝： | 帶卷 (TR) |
Automotive Multioutput Voltage Regulator
A8450
10
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
low, ENB acts as a single reset control.
Diagnostics. An open drain output, through the NFAULT pin, is
pulled low to signal to a DSP or microcontroller any of the follow-
ing fault conditions:
" V5A, the 5 V analog regulator output, is shorted to supply
" Either or both of the V5A and the V5D regulator outputs are
below their UVLO threshold, V
UVLOV5
" Device junction temperature, T
J
, exceeds the Thermal Warning
threshold, T
JTW
Charge Pump. The charge pump generates a voltage above V
BB
in
order to provide adequate gate drive for the N-channel buck switch.
A 0.1 糉 ceramic monolithic capacitor, C7, should be connected
between the VCP pin and the VBB pin, to act as a reservoir to run
the buck converter switching regulator.
V
CP
is internally monitored to ensure that the charge pump is disabled
in the case of a fault condition. In addition, a 0.1 糉 ceramic mono-
lithic capacitor, C8, should be connected between CP1 and CP2.
Power On Reset Delay. The POR block monitors the supply
voltages and provides a signal that can be used to reset a DSP or
microcontroller. A POR event is triggered by any of the following
conditions:
" Either V33 or VADJ is pulled below its UVLO threshold,
V
UVLOV33
or V
UVLOVADJ
. This occurs if the current limit on either
regulator, V
OC
, is exceeded. It also occurs if the VREG voltage
falls below V
REGMON
, due to current exceeding I
DSLIM
.
" Both input signal pins, ENB and ENBAT, are pulled low.
This immediately pulls the NPOR pin low, indicating that the
device is beginning a power-off sequence. In addition, the buck
converter switching regulator is disabled, and the VREG supply
begins to ramp down. The rate at which V
REG
decays is depen-
dent on the total current draw, I
LOAD
, and value of the output
capacitors (C1, C2, C3, and C4).
" V
REG
drops below its UVLO threshold, V
UVLOVREG
.
" During any normal power-on, V
OUTVADJ
falls below
V
UVLOVADJ
, triggering a POR.
An open drain output, through the NPOR pin, is provided to signal a
POR event to the DSP or microcontroller. The reset occurs after an
adjustable delay, t
POR
, set by an external capacitor, C9, connected
to the CPOR pin. The value of t
POR
(ms) is calculated using the
following formula
t
POR
= 2.13
?/DIV>
10
5
?
C
CPOR
where C
CPOR
(糉) is the value of the C9 capacitor.
A POR can be forced without a significant drop in the supply volt-
age, V
REG
, by pulsing low both the ENB and the ENBAT pins.
However, pulse duration should be short enough so that V
REG
does
not drop significantly.
Thermal Shutdown. When the device junction temperature, T
J
,
is sensed to be at T
JTSD
(H15癈 higher than the thermal warning
temperature, T
JTW
), a fault is indicated at the NFAULT pin. At the
same time, a thermal shutdown circuit disables the buck converter,
protecting the A8450 from damage.
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