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參數資料
| 型號： | A82596SX |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | HIGH-PERFORMANCE 32-BIT LOCAL AREA NETWORK COPROCESSOR |
| 中文描述： | 1 CHANNEL(S), 20M bps, LOCAL AREA NETWORK CONTROLLER, CPGA132 |
| 封裝： | CERAMIC, PGA-132 |
| 文件頁數： | 1/77頁 |
| 文件大小： | 787K |
| 代理商： | A82596SX |
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*
Other brands and names are the property of their respective owners.
Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or
copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make
changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.
November 1995
COPYRIGHT
INTEL CORPORATION, 1996
Order Number: 290219-006
82596DX AND 82596SX
HIGH-PERFORMANCE 32-BIT LOCAL
AREA NETWORK COPROCESSOR
Y
Performs Complete CSMA/CD Medium
Access Control (MAC) FunctionsD
Independently of CPU
D IEEE 802.3 (EOC) Frame Delimiting
Y
Supports Industry Standard LANs
D IEEE TYPE 10BASE-T (TPE),
IEEE TYPE 10BASE5 (Ethernet
*
),
IEEE TYPE 10BASE2 (Cheapernet),
IEEE TYPE 1BASE5 (StarLAN),
and the Proposed Standard
TYPE 10BASE-F
D Proprietary CSMA/CD Networks Up
to 20 Mb/s
Y
On-Chip Memory Management
D Automatic Buffer Chaining
D Buffer Reclamation after Receipt of
Bad Frames; Optional Save Bad
Frames
D 32-Bit Segmented or Linear (Flat)
Memory Addressing Formats
Y
82586 Software Compatible
Y
Optimized CPU Interface
D 82596DX Bus Interface Optimized to
Intel’s 32-Bit i386
TM
DX
D 82596SX Bus Interface Optimized to
TM
SX
D Supports Big Endian and Little
Endian Byte Ordering
Y
High-Performance 16-/32-Bit Bus
Master Interface
D 66-MB/s Bus Bandwidth
D 33-MHz Clock, Two Clocks Per
Transfer
D Bus Throttle Timers
D Transfers Data at 100% of Serial
Bandwidth
D 128-Byte Receive FIFO, 64-Byte
Transmit FIFO
Y
Network Management and Diagnostics
D Monitor Mode
D 32-Bit Statistical Counters
Y
Self-Test Diagnostics
Y
Configurable Initialization Root for Data
Structures
Y
High-Speed, 5-V, CHMOS
**
IV
Technology
Y
132-Pin Plastic Quad Flat Pack (PQFP)
and PGA Package
(See Packaging Specifications Order Number: 240800-001,
Package Type KU and A)
i386
TM
is a trademark of Intel Corporation
*
Ethernet is a registered trademark of Xerox Corporation.
**
CHMOS is a patented process of Intel Corporation.
290219–1
Figure 1. 82596DX/SX Block Diagram
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