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| 型號： | A6841SLW-T |
| 廠商： | Allegro MicroSystems, Inc. |
| 英文描述： | DABiC-5 8-Bit Serial Input Latched Sink Drivers |
| 中文描述： | 達比奇- 5 8位串行輸入鎖存灌電流驅(qū)動器 |
| 文件頁數(shù)： | 3/10頁 |
| 文件大?。?/td> | 248K |
| 代理商： | A6841SLW-T |
3
Worcester, Massachusetts 01615-0036 (508) 853-5000
115 Northeast Cutoff, Box 15036
www.allegromicro.com
A6841
DABiC-5 8-Bit Serial Input Latched Sink Drivers
D
2
ELECTRICAL CHARACTERISTICS
1
Unless otherwise noted: T
A
= 25°C, V
ee
= 0 V, logic supply operating
voltage V
dd
= 3.0 V to 5.5 V
Characteristic
Output Leakage Current
Output Sustaining Voltage
Symbol
I
CEX
V
CE(SUS)
Test Conditions
V
OUT
= 50 V
I
OUT
= 350 mA, L = 3 mH
I
OUT
= 100 mA
I
OUT
= 200 mA
I
OUT
= 350 mA
V
dd
= 3.3 V
Min.
Typ.
V
dd
= 5 V
Typ.
Units
μ
A
V
V
V
V
V
V
k
Ω
V
V
MHz
mA
Max. Min.
Max.
–
35
–
–
–
2.2
–
50
2.8
–
10
–
–
–
–
–
–
–
–
–
10
–
1.1
1.3
1.6
–
1.1
–
–
0.3
–
2.0
–
35
–
–
–
3.3
–
50
4.5
–
10
–
–
–
–
–
–
–
–
–
10
–
1.1
1.3
1.6
–
1.7
–
–
0.3
–
2.0
Collector–Emitter Saturation
Voltage
V
CE(SAT)
Input Voltage
V
IN(1)
V
IN(0)
R
IN
V
OUT(1)
V
OUT(0)
f
c
I
DD(1)
Input Resistance
Serial Data Output Voltage
I
OUT
= –200
μ
A
I
OUT
= 200
μ
A
3.05
0.15
–
–
4.75
0.15
–
–
Maximum Clock Frequency
2
Logic Supply Current
One output on, OE = L, ST = H
All outputs off, OE = H, ST = H,
P1 through P8 = L
V
r
= 50 V
I
f
= 350 mA
V
CC
= 50 V, R1 = 500
Ω
, C1
≤
30 pF
V
CC
= 50 V, R1 = 500
Ω
, C1
≤
30 pF
V
CC
= 50 V, R1 = 500
Ω
, C1
≤
30 pF
V
CC
= 50 V, R1 = 500
Ω
, C1
≤
30 pF
V
CC
= 50 V, R1 = 500
Ω
, C1
≤
30 pF
V
CC
= 50 V, R1 = 500
Ω
, C1
≤
30 pF
I
OUT
= ±200
μ
A
I
DD(0)
–
–
100
–
–
100
μ
A
Clamp Diode Leakage Current
Clamp Diode Forward Voltage
I
r
V
f
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
50
50
2
1.0
1.0
1.0
1.0
1.0
1.0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
50
2
1.0
1.0
1.0
1.0
1.0
1.0
–
μ
A
V
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
ns
Output Enable-to-Output Delay
t
dis(BQ)
t
en(BQ)
t
p(STH-QL)
t
p(STH-QH)
t
f
t
r
t
p(CH-SQX)
Strobe-to-Output Delay
Output Fall Time
Output Rise Time
Clock-to-Serial Data Out Delay
1
Positive (negative) current is de
fi
ned as conventional current going into (coming out of) the speci
fi
ed device pin.
2
Operation at a clock frequency greater than the speci
fi
ed minimum value is possible but not warran
teed.
50
Serial
Data
Input
Shift Register Contents
Serial
Data
Output
Latch Contents
Output
Enable
Input
Output Contents
Clock
Input
Strobe
Input
I
1
I
2
I
3
...
I
8
I
1
I
2
I
3
...
I
8
I
1
I
2
I
3
... I
8
R
7
R
7
R
1
R
2
R
3
...
R
8
R
8
X
X
X
...
X
X
X
L
R
1
R
2
...
R
7
L
L
R
1
R
2
R
3
...
R
8
P
1
P
2
P
3
...
P
8
P
8
P
1
P
2
P
3
...
P
8
1
P
2
P
3
... P
8
X
X
X
...
X
L
P
H
H
H
H
H
R
1
R
2
...
R
7
H
H
H
...
Truth Table
L = Low Logic Level
H = High Logic Level
X = Irrelevant
P = Present State
R = Previous State
OE = Output Enable
ST = Strobe
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